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authorGabe Black <gblack@eecs.umich.edu>2006-12-06 05:54:16 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-12-06 05:54:16 -0500
commit6456cb535cce8b35c36fa0366fc8766ecffbbf44 (patch)
tree3c49848e00e2988d0e18970905a21165abd15478 /src/cpu/o3/lsq_unit_impl.hh
parent20340b5e26e05edd364eda5f69949cc8f957921b (diff)
downloadgem5-6456cb535cce8b35c36fa0366fc8766ecffbbf44.tar.xz
Added in endianness conversion on memory accesses as the data goes out. This will break the checker!
--HG-- extra : convert_revision : b8191cab09ab8f3ced05693293f058382319ed8e
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 4facea9f9..379724166 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -596,7 +596,11 @@ LSQUnit<Impl>::writebackStores()
assert(!inst->memData);
inst->memData = new uint8_t[64];
- memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
+
+ TheISA::IntReg convertedData =
+ TheISA::htog(storeQueue[storeWBIdx].data);
+
+ memcpy(inst->memData, (uint8_t *)&convertedData,
req->getSize());
PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);