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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-04-14 05:45:55 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-04-14 05:45:55 -0400 |
commit | 750f33a90194f3f827ef887fb7e151235e61c919 (patch) | |
tree | 0146b730df44c6be8a77ac6ab86795558e394d22 /src/cpu/o3/lsq_unit_impl.hh | |
parent | dccca0d3a9c985972d3d603190e62899d03825e8 (diff) | |
download | gem5-750f33a90194f3f827ef887fb7e151235e61c919.tar.xz |
MEM: Remove the Broadcast destination from the packet
This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.
Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).
The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.
In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
-rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 2de349242..f4182e30d 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -823,13 +823,13 @@ LSQUnit<Impl>::writebackStores() if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { // Build a single data packet if the store isn't split. - data_pkt = new Packet(req, command, Packet::Broadcast); + data_pkt = new Packet(req, command); data_pkt->dataStatic(inst->memData); data_pkt->senderState = state; } else { // Create two packets if the store is split in two. - data_pkt = new Packet(sreqLow, command, Packet::Broadcast); - snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); + data_pkt = new Packet(sreqLow, command); + snd_data_pkt = new Packet(sreqHigh, command); data_pkt->dataStatic(inst->memData); snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); |