Add in support for LL/SC in the O3 CPU. Needs to be fully tested.

src/cpu/base_dyn_inst.hh:
    Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code).
src/cpu/base_dyn_inst_impl.hh:
    Add variable to track if the result of the instruction should be recorded.
src/cpu/o3/alpha/cpu_impl.hh:
    Clear lock flag upon hwrei.
src/cpu/o3/lsq_unit.hh:
    Use ISA specified handling of locked reads.
src/cpu/o3/lsq_unit_impl.hh:
    Use ISA specified handling of locked writes.

--HG--
extra : convert_revision : 1f5c789c35deb4b016573c02af4aab60d726c0e5

1 files changed, 19 insertions, 21 deletions

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 3f9db912f..05b784a1b 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -29,6 +29,7 @@
  *          Korey Sewell
  */
 
+#include "arch/locked_mem.hh"
 #include "config/use_checker.hh"
 
 #include "cpu/o3/lsq.hh"
@@ -614,27 +615,24 @@ LSQUnit<Impl>::writebackStores()
 
         // @todo: Remove this SC hack once the memory system handles it.
         if (req->isLocked()) {
-            if (req->isUncacheable()) {
-                req->setScResult(2);
-            } else {
-                if (cpu->lockFlag) {
-                    req->setScResult(1);
-                    DPRINTF(LSQUnit, "Store conditional [sn:%lli] succeeded.",
-                            inst->seqNum);
-                } else {
-                    req->setScResult(0);
-                    // Hack: Instantly complete this store.
-//                    completeDataAccess(data_pkt);
-                    DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed.  "
-                            "Instantly completing it.\n",
-                            inst->seqNum);
-                    WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
-                    wb->schedule(curTick + 1);
-                    delete state;
-                    completeStore(storeWBIdx);
-                    incrStIdx(storeWBIdx);
-                    continue;
-                }
+            // Disable recording the result temporarily.  Writing to
+            // misc regs normally updates the result, but this is not
+            // the desired behavior when handling store conditionals.
+            inst->recordResult = false;
+            bool success = TheISA::handleLockedWrite(inst.get(), req);
+            inst->recordResult = true;
+
+            if (!success) {
+                // Instantly complete this store.
+                DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed.  "
+                        "Instantly completing it.\n",
+                        inst->seqNum);
+                WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
+                wb->schedule(curTick + 1);
+                delete state;
+                completeStore(storeWBIdx);
+                incrStIdx(storeWBIdx);
+                continue;
             }
         } else {
             // Non-store conditionals do not need a writeback.