diff options
author | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-03-09 09:59:27 -0500 |
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committer | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-03-09 09:59:27 -0500 |
commit | 043709fdfab3b6c46f6ef95d1f642cd3c06ee20a (patch) | |
tree | ef8bab03f4260b67b57b00844d0245ca1e849ea0 /src/cpu/o3/lsq_unit_impl.hh | |
parent | df05ffab1289b26aab2a0eb71ee55dcb7f42e5e9 (diff) | |
download | gem5-043709fdfab3b6c46f6ef95d1f642cd3c06ee20a.tar.xz |
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files. Also merges with the SE/FS changes.
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
-rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 21 |
1 files changed, 8 insertions, 13 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index facd88597..d0a630f6d 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -45,6 +45,7 @@ #include "arch/locked_mem.hh" #include "base/str.hh" #include "config/the_isa.hh" +#include "cpu/checker/cpu.hh" #include "cpu/o3/lsq.hh" #include "cpu/o3/lsq_unit.hh" #include "debug/Activity.hh" @@ -53,10 +54,6 @@ #include "mem/packet.hh" #include "mem/request.hh" -#if USE_CHECKER -#include "cpu/checker/cpu.hh" -#endif - template<class Impl> LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, LSQUnit *lsq_ptr) @@ -871,11 +868,12 @@ LSQUnit<Impl>::writebackStores() inst->seqNum); WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); cpu->schedule(wb, curTick() + 1); -#if USE_CHECKER - // Make sure to set the LLSC data for verification - inst->reqToVerify->setExtraData(0); - inst->completeAcc(data_pkt); -#endif + if (cpu->checker) { + // Make sure to set the LLSC data for verification + // if checker is loaded + inst->reqToVerify->setExtraData(0); + inst->completeAcc(data_pkt); + } completeStore(storeWBIdx); incrStIdx(storeWBIdx); continue; @@ -1083,11 +1081,10 @@ LSQUnit<Impl>::storePostSend(PacketPtr pkt) // only works so long as the checker doesn't try to // verify the value in memory for stores. storeQueue[storeWBIdx].inst->setCompleted(); -#if USE_CHECKER + if (cpu->checker) { cpu->checker->verify(storeQueue[storeWBIdx].inst); } -#endif } if (needsTSO) { @@ -1174,11 +1171,9 @@ LSQUnit<Impl>::completeStore(int store_idx) // Tell the checker we've completed this instruction. Some stores // may get reported twice to the checker, but the checker can // handle that case. -#if USE_CHECKER if (cpu->checker) { cpu->checker->verify(storeQueue[store_idx].inst); } -#endif } template <class Impl> |