diff options
author | Kevin Lim <ktlim@umich.edu> | 2006-10-23 14:32:35 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-10-23 14:32:35 -0400 |
commit | ce4531c0794ee57c0029bc905802a7856832d941 (patch) | |
tree | 4d6c87eae2b07f350dc7aa26454e9304aec457dd /src/cpu/o3/lsq_unit_impl.hh | |
parent | ef8b7713ca1b6120ae4e851877f2a9ce71296219 (diff) | |
parent | 4ccccfef7144d6c36acdb780395141e5d71890c1 (diff) | |
download | gem5-ce4531c0794ee57c0029bc905802a7856832d941.tar.xz |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
--HG--
extra : convert_revision : 161c35ade82f2471e605d948dca56cfa216693fd
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
-rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 40 |
1 files changed, 19 insertions, 21 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index d940d7cb3..8a63ff011 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -29,6 +29,7 @@ * Korey Sewell */ +#include "arch/locked_mem.hh" #include "config/use_checker.hh" #include "cpu/o3/lsq.hh" @@ -614,27 +615,24 @@ LSQUnit<Impl>::writebackStores() // @todo: Remove this SC hack once the memory system handles it. if (req->isLocked()) { - if (req->isUncacheable()) { - req->setScResult(2); - } else { - if (cpu->lockFlag) { - req->setScResult(1); - DPRINTF(LSQUnit, "Store conditional [sn:%lli] succeeded.", - inst->seqNum); - } else { - req->setScResult(0); - // Hack: Instantly complete this store. -// completeDataAccess(data_pkt); - DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " - "Instantly completing it.\n", - inst->seqNum); - WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); - wb->schedule(curTick + 1); - delete state; - completeStore(storeWBIdx); - incrStIdx(storeWBIdx); - continue; - } + // Disable recording the result temporarily. Writing to + // misc regs normally updates the result, but this is not + // the desired behavior when handling store conditionals. + inst->recordResult = false; + bool success = TheISA::handleLockedWrite(inst.get(), req); + inst->recordResult = true; + + if (!success) { + // Instantly complete this store. + DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " + "Instantly completing it.\n", + inst->seqNum); + WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); + wb->schedule(curTick + 1); + delete state; + completeStore(storeWBIdx); + incrStIdx(storeWBIdx); + continue; } } else { // Non-store conditionals do not need a writeback. |