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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:39 -0400 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:39 -0400 |
| commit | 4f13f676aa71efaaae2fcd2587cf032a1d70f774 (patch) | |
| tree | 1a8dec232d4bd77df2e773e824510959c643d091 /src/cpu/o3/mem_dep_unit.hh | |
| parent | 283935a6f0a17afe4574cc3c50c043515c866dfa (diff) | |
| download | gem5-4f13f676aa71efaaae2fcd2587cf032a1d70f774.tar.xz | |
cpu: Fix cache blocked load behavior in o3 cpu
This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than
flushing the entire pipeline, this patch replays loads once the cache becomes
unblocked.
Additionally, deferred memory instructions (loads which had conflicting stores),
when replayed would not respect the number of functional units (only respected
issue width). This patch also corrects that.
Improvements over 20% have been observed on a microbenchmark designed to
exercise this behavior.
Diffstat (limited to 'src/cpu/o3/mem_dep_unit.hh')
| -rw-r--r-- | src/cpu/o3/mem_dep_unit.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh index 989d36ea1..a42aa13ce 100644 --- a/src/cpu/o3/mem_dep_unit.hh +++ b/src/cpu/o3/mem_dep_unit.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 ARM Limited + * Copyright (c) 2012, 2014 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -134,7 +134,7 @@ class MemDepUnit /** Replays all instructions that have been rescheduled by moving them to * the ready list. */ - void replay(DynInstPtr &inst); + void replay(); /** Completes a memory instruction. */ void completed(DynInstPtr &inst); |