diff options
author | Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> | 2017-02-06 11:10:06 +0000 |
---|---|---|
committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2018-11-16 10:39:03 +0000 |
commit | 0c50a0b4fe3956f9d2e08e75d47c9cbd79bf0268 (patch) | |
tree | 7679abe2343e0504c93eb73d09635d546a211455 /src/cpu/o3/mem_dep_unit.hh | |
parent | 338a173e822298bd22741342a7b24352450afdd1 (diff) | |
download | gem5-0c50a0b4fe3956f9d2e08e75d47c9cbd79bf0268.tar.xz |
cpu: Fix the usage of const DynInstPtr
Summary: Usage of const DynInstPtr& when possible and introduction of
move operators to RefCountingPtr.
In many places, scoped references to dynamic instructions do a copy of
the DynInstPtr when a reference would do. This is detrimental to
performance. On top of that, in case there is a need for reference
tracking for debugging, the redundant copies make the process much more
painful than it already is.
Also, from the theoretical point of view, a function/method that
defines a convenience name to access an instruction should not be
considered an owner of the data, i.e., doing a copy and not a reference
is not justified.
On a related topic, C++11 introduces move semantics, and those are
useful when, for example, there is a class modelling a HW structure that
contains a list, and has a getHeadOfList function, to prevent doing a
copy to an internal variable -> update pointer, remove from the list ->
update pointer, return value making a copy to the assined variable ->
update pointer, destroy the returned value -> update pointer.
Change-Id: I3bb46c20ef23b6873b469fd22befb251ac44d2f6
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13105
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3/mem_dep_unit.hh')
-rw-r--r-- | src/cpu/o3/mem_dep_unit.hh | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh index ffe66be6b..24f5c20ee 100644 --- a/src/cpu/o3/mem_dep_unit.hh +++ b/src/cpu/o3/mem_dep_unit.hh @@ -85,6 +85,7 @@ class MemDepUnit public: typedef typename Impl::DynInstPtr DynInstPtr; + typedef typename Impl::DynInstConstPtr DynInstConstPtr; /** Empty constructor. Must call init() prior to using in this case. */ MemDepUnit(); @@ -117,22 +118,22 @@ class MemDepUnit void setIQ(InstructionQueue<Impl> *iq_ptr); /** Inserts a memory instruction. */ - void insert(DynInstPtr &inst); + void insert(const DynInstPtr &inst); /** Inserts a non-speculative memory instruction. */ - void insertNonSpec(DynInstPtr &inst); + void insertNonSpec(const DynInstPtr &inst); /** Inserts a barrier instruction. */ - void insertBarrier(DynInstPtr &barr_inst); + void insertBarrier(const DynInstPtr &barr_inst); /** Indicate that an instruction has its registers ready. */ - void regsReady(DynInstPtr &inst); + void regsReady(const DynInstPtr &inst); /** Indicate that a non-speculative instruction is ready. */ - void nonSpecInstReady(DynInstPtr &inst); + void nonSpecInstReady(const DynInstPtr &inst); /** Reschedules an instruction to be re-executed. */ - void reschedule(DynInstPtr &inst); + void reschedule(const DynInstPtr &inst); /** Replays all instructions that have been rescheduled by moving them to * the ready list. @@ -140,13 +141,13 @@ class MemDepUnit void replay(); /** Completes a memory instruction. */ - void completed(DynInstPtr &inst); + void completed(const DynInstPtr &inst); /** Completes a barrier instruction. */ - void completeBarrier(DynInstPtr &inst); + void completeBarrier(const DynInstPtr &inst); /** Wakes any dependents of a memory instruction. */ - void wakeDependents(DynInstPtr &inst); + void wakeDependents(const DynInstPtr &inst); /** Squashes all instructions up until a given sequence number for a * specific thread. @@ -154,10 +155,11 @@ class MemDepUnit void squash(const InstSeqNum &squashed_num, ThreadID tid); /** Indicates an ordering violation between a store and a younger load. */ - void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); + void violation(const DynInstPtr &store_inst, + const DynInstPtr &violating_load); /** Issues the given instruction */ - void issue(DynInstPtr &inst); + void issue(const DynInstPtr &inst); /** Debugging function to dump the lists of instructions. */ void dumpLists(); @@ -176,7 +178,7 @@ class MemDepUnit class MemDepEntry { public: /** Constructs a memory dependence entry. */ - MemDepEntry(DynInstPtr &new_inst) + MemDepEntry(const DynInstPtr &new_inst) : inst(new_inst), regsReady(false), memDepReady(false), completed(false), squashed(false) { @@ -232,7 +234,7 @@ class MemDepUnit }; /** Finds the memory dependence entry in the hash map. */ - inline MemDepEntryPtr &findInHash(const DynInstPtr &inst); + inline MemDepEntryPtr &findInHash(const DynInstConstPtr& inst); /** Moves an entry to the ready list. */ inline void moveToReady(MemDepEntryPtr &ready_inst_entry); |