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author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/cpu/o3/probe | |
parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/cpu/o3/probe')
-rw-r--r-- | src/cpu/o3/probe/elastic_trace.cc | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/o3/probe/elastic_trace.cc b/src/cpu/o3/probe/elastic_trace.cc index c97bf7877..05b16805f 100644 --- a/src/cpu/o3/probe/elastic_trace.cc +++ b/src/cpu/o3/probe/elastic_trace.cc @@ -262,15 +262,15 @@ ElasticTrace::updateRegDep(const DynInstPtr &dyn_inst) for (int dest_idx = 0; dest_idx < max_regs; dest_idx++) { // For data dependency tracking the register must be an int, float or // CC register and not a Misc register. - TheISA::RegIndex dest_reg = dyn_inst->destRegIdx(dest_idx); - if (regIdxToClass(dest_reg) != MiscRegClass) { - // Get the physical register index of the i'th destination register. - dest_reg = dyn_inst->renamedDestRegIdx(dest_idx); - if (dest_reg != TheISA::ZeroReg) { - DPRINTFR(ElasticTrace, "[sn:%lli] Update map for dest reg %i\n", - seq_num, dest_reg); - physRegDepMap[dest_reg] = seq_num; - } + RegId dest_reg = dyn_inst->destRegIdx(dest_idx); + if (dest_reg.isRenameable() && + !dest_reg.isZeroReg()) { + // Get the physical register index of the i'th destination + // register. + PhysRegIndex phys_dest_reg = dyn_inst->renamedDestRegIdx(dest_idx); + DPRINTFR(ElasticTrace, "[sn:%lli] Update map for dest reg %i\n", + seq_num, dest_reg.regIdx); + physRegDepMap[phys_dest_reg] = seq_num; } } maxPhysRegDepMapSize = std::max(physRegDepMap.size(), |