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authorNilay Vaish <nilay@cs.wisc.edu>2015-07-26 10:21:20 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-07-26 10:21:20 -0500
commit608641e23c7f2288810c3f23a1a63790b664f2ab (patch)
tree0656aaf9653e8d263f5daac0d5f0fe3190193ae5 /src/cpu/o3/regfile.cc
parent6e354e82d9395b20f5f148cd545d0666b626e8ac (diff)
downloadgem5-608641e23c7f2288810c3f23a1a63790b664f2ab.tar.xz
cpu: implements vector registers
This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now.
Diffstat (limited to 'src/cpu/o3/regfile.cc')
-rw-r--r--src/cpu/o3/regfile.cc26
1 files changed, 22 insertions, 4 deletions
diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc
index 96ce44bdd..a7476c5ec 100644
--- a/src/cpu/o3/regfile.cc
+++ b/src/cpu/o3/regfile.cc
@@ -37,15 +37,20 @@
PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
unsigned _numPhysicalFloatRegs,
- unsigned _numPhysicalCCRegs)
+ unsigned _numPhysicalCCRegs,
+ unsigned _numPhysicalVectorRegs)
: intRegFile(_numPhysicalIntRegs),
floatRegFile(_numPhysicalFloatRegs),
ccRegFile(_numPhysicalCCRegs),
+ vectorRegFile(_numPhysicalVectorRegs),
baseFloatRegIndex(_numPhysicalIntRegs),
baseCCRegIndex(_numPhysicalIntRegs + _numPhysicalFloatRegs),
+ baseVectorRegIndex(_numPhysicalIntRegs + _numPhysicalFloatRegs
+ + _numPhysicalCCRegs),
totalNumRegs(_numPhysicalIntRegs
+ _numPhysicalFloatRegs
- + _numPhysicalCCRegs)
+ + _numPhysicalCCRegs
+ + _numPhysicalVectorRegs)
{
if (TheISA::NumCCRegs == 0 && _numPhysicalCCRegs != 0) {
// Just make this a warning and go ahead and allocate them
@@ -53,6 +58,13 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
warn("Non-zero number of physical CC regs specified, even though\n"
" ISA does not use them.\n");
}
+
+ if (TheISA::NumVectorRegs == 0 && _numPhysicalVectorRegs != 0) {
+ // Just make this a warning and go ahead and allocate them
+ // anyway, to keep from having to add checks everywhere
+ warn("Non-zero number of physical vector regs specified, even though\n"
+ " ISA does not use them.\n");
+ }
}
@@ -73,9 +85,15 @@ PhysRegFile::initFreeList(UnifiedFreeList *freeList)
freeList->addFloatReg(reg_idx++);
}
- // The rest of the registers are the condition-code physical
+ // The next batch of registers are the condition-code physical
// registers; put them onto the condition-code free list.
- while (reg_idx < totalNumRegs) {
+ while (reg_idx < baseVectorRegIndex) {
freeList->addCCReg(reg_idx++);
}
+
+ // The rest of the registers are the vector physical
+ // registers; put them onto the vector free list.
+ while (reg_idx < totalNumRegs) {
+ freeList->addVectorReg(reg_idx++);
+ }
}