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authorKevin Lim <ktlim@umich.edu>2006-05-31 11:34:42 -0400
committerKevin Lim <ktlim@umich.edu>2006-05-31 11:34:42 -0400
commitd4b73086b6b0856c28433b55c8dd5c7b56a1b6df (patch)
treeb54cb10579c6c5788fc09e7abd5d3a0ab1dd533c /src/cpu/o3/regfile.hh
parentd77d39daee5c3ba8483d58911a1d5b12c4707040 (diff)
parent4a5b51b516853c9fcaabc44caacdd7e8e93dc0ef (diff)
downloadgem5-d4b73086b6b0856c28433b55c8dd5c7b56a1b6df.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem --HG-- extra : convert_revision : 3d951bbeee0178de47e1bdbe704808544bfe732e
Diffstat (limited to 'src/cpu/o3/regfile.hh')
-rw-r--r--src/cpu/o3/regfile.hh116
1 files changed, 53 insertions, 63 deletions
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index a5cfa8f3c..3350903db 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -26,10 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_REGFILE_HH__
-#define __CPU_O3_CPU_REGFILE_HH__
-
-// @todo: Destructor
+#ifndef __CPU_O3_REGFILE_HH__
+#define __CPU_O3_REGFILE_HH__
#include "arch/isa_traits.hh"
#include "arch/faults.hh"
@@ -42,11 +40,14 @@
#endif
-// This really only depends on the ISA, and not the Impl. It might be nicer
-// to see if I can make it depend on nothing...
-// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,
-// and should go in the AlphaFullCPU.
+#include <vector>
+/**
+ * Simple physical register file class.
+ * This really only depends on the ISA, and not the Impl. Things that are
+ * in the ifdef FULL_SYSTEM are pretty dependent on the ISA, and probably
+ * should go in the AlphaFullCPU.
+ */
template <class Impl>
class PhysRegFile
{
@@ -55,19 +56,18 @@ class PhysRegFile
typedef TheISA::FloatReg FloatReg;
typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
+ // Note that most of the definitions of the IntReg, FloatReg, etc. exist
+ // within the Impl/ISA class and not within this PhysRegFile class.
- //Note that most of the definitions of the IntReg, FloatReg, etc. exist
- //within the Impl/ISA class and not within this PhysRegFile class.
-
- //Will need some way to allow stuff like swap_palshadow to access the
- //correct registers. Might require code changes to swap_palshadow and
- //other execution contexts.
-
- //Will make these registers public for now, but they probably should
- //be private eventually with some accessor functions.
+ // Will make these registers public for now, but they probably should
+ // be private eventually with some accessor functions.
public:
typedef typename Impl::FullCPU FullCPU;
+ /**
+ * Constructs a physical register file with the specified amount of
+ * integer and floating point registers.
+ */
PhysRegFile(unsigned _numPhysicalIntRegs,
unsigned _numPhysicalFloatRegs);
@@ -80,6 +80,7 @@ class PhysRegFile
// void serialize(std::ostream &os);
// void unserialize(Checkpoint *cp, const std::string &section);
+ /** Reads an integer register. */
uint64_t readIntReg(PhysRegIndex reg_idx)
{
assert(reg_idx < numPhysicalIntRegs);
@@ -104,6 +105,7 @@ class PhysRegFile
return floatReg;
}
+ /** Reads a floating point register (double precision). */
FloatReg readFloatReg(PhysRegIndex reg_idx)
{
// Remove the base Float reg dependency.
@@ -119,6 +121,7 @@ class PhysRegFile
return floatReg;
}
+ /** Reads a floating point register as an integer. */
FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
{
// Remove the base Float reg dependency.
@@ -149,6 +152,7 @@ class PhysRegFile
return floatRegBits;
}
+ /** Sets an integer register to the given value. */
void setIntReg(PhysRegIndex reg_idx, uint64_t val)
{
assert(reg_idx < numPhysicalIntRegs);
@@ -156,9 +160,11 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n",
int(reg_idx), val);
- intRegFile[reg_idx] = val;
+ if (reg_idx != TheISA::ZeroReg)
+ intRegFile[reg_idx] = val;
}
+ /** Sets a single precision floating point register to the given value. */
void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
{
// Remove the base Float reg dependency.
@@ -169,9 +175,11 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
int(reg_idx), (double)val);
- floatRegFile.setReg(reg_idx, val, width);
+ if (reg_idx != TheISA::ZeroReg)
+ floatRegFile.setReg(reg_idx, val, width);
}
+ /** Sets a double precision floating point register to the given value. */
void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
{
// Remove the base Float reg dependency.
@@ -182,9 +190,11 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
int(reg_idx), (double)val);
- floatRegFile.setReg(reg_idx, val);
+ if (reg_idx != TheISA::ZeroReg)
+ floatRegFile.setReg(reg_idx, val);
}
+ /** Sets a floating point register to the given integer value. */
void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
{
// Remove the base Float reg dependency.
@@ -207,79 +217,59 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
int(reg_idx), (uint64_t)val);
-
- floatRegFile.setRegBits(reg_idx, val);
- }
-
- uint64_t readPC()
- {
- return pc;
- }
-
- void setPC(uint64_t val)
- {
- pc = val;
}
- void setNextPC(uint64_t val)
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
+ unsigned thread_id)
{
- npc = val;
+ return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
+ cpu->xcBase(thread_id));
}
- //Consider leaving this stuff and below in some implementation specific
- //file as opposed to the general register file. Or have a derived class.
- MiscReg readMiscReg(int misc_reg)
+ Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
{
- // Dummy function for now.
- // @todo: Fix this once proxy XC is used.
- return 0;
+ return miscRegs[thread_id].setReg(misc_reg, val);
}
- Fault setMiscReg(int misc_reg, const MiscReg &val)
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
+ unsigned thread_id)
{
- // Dummy function for now.
- // @todo: Fix this once proxy XC is used.
- return NoFault;
+ return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
+ cpu->xcBase(thread_id));
}
#if FULL_SYSTEM
int readIntrFlag() { return intrflag; }
+ /** Sets an interrupt flag. */
void setIntrFlag(int val) { intrflag = val; }
#endif
- // These should be private eventually, but will be public for now
- // so that I can hack around the initregs issue.
public:
/** (signed) integer register file. */
- IntReg *intRegFile;
+ std::vector<IntReg> intRegFile;
/** Floating point register file. */
- FloatReg *floatRegFile;
+ std::vector<FloatReg> floatRegFile;
/** Miscellaneous register file. */
- MiscRegFile miscRegs;
-
- /** Program counter. */
- Addr pc;
-
- /** Next-cycle program counter. */
- Addr npc;
+ MiscRegFile miscRegs[Impl::MaxThreads];
#if FULL_SYSTEM
private:
- // This is ISA specifc stuff; remove it eventually once ISAImpl is used
-// IntReg palregs[NumIntRegs]; // PAL shadow registers
int intrflag; // interrupt flag
- bool pal_shadow; // using pal_shadow registers
#endif
private:
+ /** CPU pointer. */
FullCPU *cpu;
public:
+ /** Sets the CPU pointer. */
void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; }
+ /** Number of physical integer registers. */
unsigned numPhysicalIntRegs;
+ /** Number of physical floating point registers. */
unsigned numPhysicalFloatRegs;
};
@@ -289,11 +279,11 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
: numPhysicalIntRegs(_numPhysicalIntRegs),
numPhysicalFloatRegs(_numPhysicalFloatRegs)
{
- intRegFile = new IntReg[numPhysicalIntRegs];
- floatRegFile = new FloatReg[numPhysicalFloatRegs];
+ intRegFile.resize(numPhysicalIntRegs);
+ floatRegFile.resize(numPhysicalFloatRegs);
- memset(intRegFile, 0, sizeof(*intRegFile));
- memset(floatRegFile, 0, sizeof(*floatRegFile));
+ //memset(intRegFile, 0, sizeof(*intRegFile));
+ //memset(floatRegFile, 0, sizeof(*floatRegFile));
}
-#endif // __CPU_O3_CPU_REGFILE_HH__
+#endif