check loads using tainted registers, set USL dst as tainted

1 files changed, 18 insertions, 0 deletions

diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 00b4ef045..4d54acc2f 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -199,10 +199,28 @@ class PhysRegFile
         miscTaintMap[idx] = true;
         break;
       default:
+        warn_once("taint for vector registers not supported yet\n");
         break;
       }
     }
 
+    bool regTainted(PhysRegIdPtr phys_reg) {
+      RegIndex idx = phys_reg->index();
+      switch (phys_reg->classValue()) {
+      case IntRegClass:
+        return intTaintMap[idx];
+      case FloatRegClass:
+        return floatTaintMap[idx];
+      case CCRegClass:
+        return ccTaintMap[idx];
+      case MiscRegClass:
+        return miscTaintMap[idx];
+      default:
+        warn_once("taint for vector registers not supported yet\n");
+        return false;
+      }
+    }
+
     /** Reads an integer register. */
     uint64_t readIntReg(PhysRegIdPtr phys_reg) const
     {