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author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
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committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/o3/regfile.hh | |
parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/o3/regfile.hh')
-rw-r--r-- | src/cpu/o3/regfile.hh | 57 |
1 files changed, 54 insertions, 3 deletions
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index bd3a4f730..8b87725ca 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -55,6 +55,7 @@ class PhysRegFile typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; + typedef TheISA::CCReg CCReg; typedef union { FloatReg d; @@ -67,6 +68,9 @@ class PhysRegFile /** Floating point register file. */ std::vector<PhysFloatReg> floatRegFile; + /** Condition-code register file. */ + std::vector<CCReg> ccRegFile; + /** * The first floating-point physical register index. The physical * register file has a single continuous index space, with the @@ -83,6 +87,12 @@ class PhysRegFile */ unsigned baseFloatRegIndex; + /** + * The first condition-code physical register index. The + * condition-code registers follow the floating-point registers. + */ + unsigned baseCCRegIndex; + /** Total number of physical registers. */ unsigned totalNumRegs; @@ -92,7 +102,8 @@ class PhysRegFile * integer and floating point registers. */ PhysRegFile(unsigned _numPhysicalIntRegs, - unsigned _numPhysicalFloatRegs); + unsigned _numPhysicalFloatRegs, + unsigned _numPhysicalCCRegs); /** * Destructor to free resources @@ -107,7 +118,11 @@ class PhysRegFile /** @return the number of floating-point physical registers. */ unsigned numFloatPhysRegs() const - { return totalNumRegs - baseFloatRegIndex; } + { return baseCCRegIndex - baseFloatRegIndex; } + + /** @return the number of condition-code physical registers. */ + unsigned numCCPhysRegs() const + { return totalNumRegs - baseCCRegIndex; } /** @return the total number of physical registers. */ unsigned totalNumPhysRegs() const { return totalNumRegs; } @@ -127,7 +142,16 @@ class PhysRegFile */ bool isFloatPhysReg(PhysRegIndex reg_idx) const { - return (baseFloatRegIndex <= reg_idx && reg_idx < totalNumRegs); + return (baseFloatRegIndex <= reg_idx && reg_idx < baseCCRegIndex); + } + + /** + * Return true if the specified physical register index + * corresponds to a condition-code physical register. + */ + bool isCCPhysReg(PhysRegIndex reg_idx) + { + return (baseCCRegIndex <= reg_idx && reg_idx < totalNumRegs); } /** Reads an integer register. */ @@ -169,6 +193,20 @@ class PhysRegFile return floatRegBits; } + /** Reads a condition-code register. */ + CCReg readCCReg(PhysRegIndex reg_idx) + { + assert(isCCPhysReg(reg_idx)); + + // Remove the base CC reg dependency. + PhysRegIndex reg_offset = reg_idx - baseCCRegIndex; + + DPRINTF(IEW, "RegFile: Access to cc register %i, has " + "data %#x\n", int(reg_idx), ccRegFile[reg_offset]); + + return ccRegFile[reg_offset]; + } + /** Sets an integer register to the given value. */ void setIntReg(PhysRegIndex reg_idx, uint64_t val) { @@ -211,6 +249,19 @@ class PhysRegFile floatRegFile[reg_offset].q = val; } + /** Sets a condition-code register to the given value. */ + void setCCReg(PhysRegIndex reg_idx, CCReg val) + { + assert(isCCPhysReg(reg_idx)); + + // Remove the base CC reg dependency. + PhysRegIndex reg_offset = reg_idx - baseCCRegIndex; + + DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n", + int(reg_idx), (uint64_t)val); + + ccRegFile[reg_offset] = val; + } }; |