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author | Iru Cai <mytbk920423@gmail.com> | 2019-04-08 10:42:39 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 15:59:17 +0800 |
commit | 57eb50e414a3aaa6e8bc96ae158af55246cb6754 (patch) | |
tree | 9d7c2d4a2598ae916d3976e6dbcc739c6b16fb59 /src/cpu/o3/regfile.hh | |
parent | c0d7cca1d9895f1c3476ce9864584eb4fb2e6ee9 (diff) | |
download | gem5-57eb50e414a3aaa6e8bc96ae158af55246cb6754.tar.xz |
implement taint propagation
Diffstat (limited to 'src/cpu/o3/regfile.hh')
-rw-r--r-- | src/cpu/o3/regfile.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 4d54acc2f..b835a7dd8 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -183,20 +183,20 @@ class PhysRegFile } /** Set a physical register as tainted */ - void setTaint(PhysRegIdPtr phys_reg) { + void setTaint(PhysRegIdPtr phys_reg, bool taintvalue) { RegIndex idx = phys_reg->index(); switch (phys_reg->classValue()) { case IntRegClass: - intTaintMap[idx] = true; + intTaintMap[idx] = taintvalue; break; case FloatRegClass: - floatTaintMap[idx] = true; + floatTaintMap[idx] = taintvalue; break; case CCRegClass: - ccTaintMap[idx] = true; + ccTaintMap[idx] = taintvalue; break; case MiscRegClass: - miscTaintMap[idx] = true; + miscTaintMap[idx] = taintvalue; break; default: warn_once("taint for vector registers not supported yet\n"); |