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author | Iru Cai <mytbk920423@gmail.com> | 2019-04-03 10:29:37 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 15:59:17 +0800 |
commit | c0d7cca1d9895f1c3476ce9864584eb4fb2e6ee9 (patch) | |
tree | 3a1cb356c61cc6366d20c46353ed494d8e49ba92 /src/cpu/o3/regfile.hh | |
parent | cb5562bb15f32e9040eccb57271d86fddc614230 (diff) | |
download | gem5-c0d7cca1d9895f1c3476ce9864584eb4fb2e6ee9.tar.xz |
check loads using tainted registers, set USL dst as tainted
Diffstat (limited to 'src/cpu/o3/regfile.hh')
-rw-r--r-- | src/cpu/o3/regfile.hh | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 00b4ef045..4d54acc2f 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -199,10 +199,28 @@ class PhysRegFile miscTaintMap[idx] = true; break; default: + warn_once("taint for vector registers not supported yet\n"); break; } } + bool regTainted(PhysRegIdPtr phys_reg) { + RegIndex idx = phys_reg->index(); + switch (phys_reg->classValue()) { + case IntRegClass: + return intTaintMap[idx]; + case FloatRegClass: + return floatTaintMap[idx]; + case CCRegClass: + return ccTaintMap[idx]; + case MiscRegClass: + return miscTaintMap[idx]; + default: + warn_once("taint for vector registers not supported yet\n"); + return false; + } + } + /** Reads an integer register. */ uint64_t readIntReg(PhysRegIdPtr phys_reg) const { |