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| author | Iru Cai <mytbk920423@gmail.com> | 2019-04-02 16:28:08 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 15:59:17 +0800 |
| commit | cb5562bb15f32e9040eccb57271d86fddc614230 (patch) | |
| tree | 27386c5b4c2ab2ff3b7e8865f1300c7c54609c2b /src/cpu/o3/regfile.hh | |
| parent | 679ca8b4cff6b683dff69a96eb8eb61716b61ad8 (diff) | |
| download | gem5-cb5562bb15f32e9040eccb57271d86fddc614230.tar.xz | |
methods to set taint
Diffstat (limited to 'src/cpu/o3/regfile.hh')
| -rw-r--r-- | src/cpu/o3/regfile.hh | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 943df35b9..00b4ef045 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -182,6 +182,27 @@ class PhysRegFile return &miscRegIds[reg_idx]; } + /** Set a physical register as tainted */ + void setTaint(PhysRegIdPtr phys_reg) { + RegIndex idx = phys_reg->index(); + switch (phys_reg->classValue()) { + case IntRegClass: + intTaintMap[idx] = true; + break; + case FloatRegClass: + floatTaintMap[idx] = true; + break; + case CCRegClass: + ccTaintMap[idx] = true; + break; + case MiscRegClass: + miscTaintMap[idx] = true; + break; + default: + break; + } + } + /** Reads an integer register. */ uint64_t readIntReg(PhysRegIdPtr phys_reg) const { |