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authorGabe Black <gblack@eecs.umich.edu>2007-05-09 20:50:46 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-05-09 20:50:46 -0700
commit4ad1b58fdd7cc9ba9704ae966a41c99fd0f1dbc9 (patch)
tree2c68db7cd94a457fff83fe8d4bd7c63a6de023c0 /src/cpu/o3/regfile.hh
parent939cbd8201a4b0dfad6a56b5d9fb68cc2b23ae73 (diff)
parentc2ac0fd89b9928f653e1485b2432cd71b455d7c5 (diff)
downloadgem5-4ad1b58fdd7cc9ba9704ae966a41c99fd0f1dbc9.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into doughnut.mwconnections.com:/home/gblack/newmem-o3-micro --HG-- extra : convert_revision : 545b9e98eb1895f4b9e782224fb6615c71ed6323
Diffstat (limited to 'src/cpu/o3/regfile.hh')
-rw-r--r--src/cpu/o3/regfile.hh4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index b5b1cd021..75d3fa6eb 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -179,7 +179,9 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
int(reg_idx), (uint64_t)val);
+#if THE_ISA == ALPHA_ISA
if (reg_idx != TheISA::ZeroReg)
+#endif
floatRegFile[reg_idx].d = val;
}
@@ -194,7 +196,9 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
int(reg_idx), (uint64_t)val);
+#if THE_ISA == ALPHA_ISA
if (reg_idx != TheISA::ZeroReg)
+#endif
floatRegFile[reg_idx].d = val;
}