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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-04-22 17:50:43 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-04-22 17:50:43 +0000 |
| commit | acc62514b1a4244182a7e5fad8ca03505389d94d (patch) | |
| tree | 29e96f23f04f19c16a9fdf1f7ef5fa9d7f23b277 /src/cpu/o3/regfile.hh | |
| parent | cea543576082ed860e8dae17519ace48e5b2c78a (diff) | |
| download | gem5-acc62514b1a4244182a7e5fad8ca03505389d94d.tar.xz | |
Make the floating point zero register special handling only apply for ALPHA.
--HG--
extra : convert_revision : 4f393a5471656b29cecbacfcb337992239775915
Diffstat (limited to 'src/cpu/o3/regfile.hh')
| -rw-r--r-- | src/cpu/o3/regfile.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index b5b1cd021..75d3fa6eb 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -179,7 +179,9 @@ class PhysRegFile DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", int(reg_idx), (uint64_t)val); +#if THE_ISA == ALPHA_ISA if (reg_idx != TheISA::ZeroReg) +#endif floatRegFile[reg_idx].d = val; } @@ -194,7 +196,9 @@ class PhysRegFile DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", int(reg_idx), (uint64_t)val); +#if THE_ISA == ALPHA_ISA if (reg_idx != TheISA::ZeroReg) +#endif floatRegFile[reg_idx].d = val; } |