diff options
author | Gabe Black <gabeblack@google.com> | 2018-11-19 17:30:06 -0800 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2018-12-22 20:55:07 +0000 |
commit | ff7fc9de6955ba3e00898eb703b3da1a15fb417c (patch) | |
tree | 48aea9cccce33e478c6dae732aed9b8e6566ee9e /src/cpu/o3/regfile.hh | |
parent | 88bbabe93f339f9db301caf43bf2cca2a0e8048c (diff) | |
download | gem5-ff7fc9de6955ba3e00898eb703b3da1a15fb417c.tar.xz |
cpu: Stop using unions to store FP registers.
These are now accessed only as integer values.
Change-Id: I21ae6537ebbcbaa02890384194ee1ce001c092bb
Reviewed-on: https://gem5-review.googlesource.com/c/14458
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/o3/regfile.hh')
-rw-r--r-- | src/cpu/o3/regfile.hh | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 2f874213f..354fe2bc5 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -79,17 +79,12 @@ class PhysRegFile private: static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; - typedef union { - FloatReg d; - FloatRegBits q; - } PhysFloatReg; - /** Integer register file. */ std::vector<IntReg> intRegFile; std::vector<PhysRegId> intRegIds; /** Floating point register file. */ - std::vector<PhysFloatReg> floatRegFile; + std::vector<FloatRegBits> floatRegFile; std::vector<PhysRegId> floatRegIds; /** Vector register file. */ @@ -191,7 +186,7 @@ class PhysRegFile { assert(phys_reg->isFloatPhysReg()); - FloatRegBits floatRegBits = floatRegFile[phys_reg->index()].q; + FloatRegBits floatRegBits = floatRegFile[phys_reg->index()]; DPRINTF(IEW, "RegFile: Access to float register %i as int, " "has data %#x\n", phys_reg->index(), @@ -294,7 +289,7 @@ class PhysRegFile phys_reg->index(), (uint64_t)val); if (!phys_reg->isZeroReg()) - floatRegFile[phys_reg->index()].q = val; + floatRegFile[phys_reg->index()] = val; } /** Sets a vector register to the given value. */ |