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| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/cpu/o3/rename.hh | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/cpu/o3/rename.hh')
| -rw-r--r-- | src/cpu/o3/rename.hh | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh index f8becc114..c0483d445 100644 --- a/src/cpu/o3/rename.hh +++ b/src/cpu/o3/rename.hh @@ -85,9 +85,6 @@ class DefaultRename typedef typename CPUPol::IEW IEW; typedef typename CPUPol::Commit Commit; - // Typedefs from the ISA. - typedef TheISA::RegIndex RegIndex; - // A deque is used to queue the instructions. Barrier insts must // be added to the front of the queue, which is the only reason for // using a deque instead of a queue. (Most other stages use a @@ -301,7 +298,7 @@ class DefaultRename * register for that arch. register, and the new physical register. */ struct RenameHistory { - RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, + RenameHistory(InstSeqNum _instSeqNum, RegId _archReg, PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) : instSeqNum(_instSeqNum), archReg(_archReg), newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg) @@ -311,7 +308,7 @@ class DefaultRename /** The sequence number of the instruction that renamed. */ InstSeqNum instSeqNum; /** The architectural register index that was renamed. */ - RegIndex archReg; + RegId archReg; /** The new physical register that the arch. register is renamed to. */ PhysRegIndex newPhysReg; /** The old physical register that the arch. register was renamed to. */ |