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author | Radhika Jagtap <radhika.jagtap@ARM.com> | 2015-12-07 16:42:15 -0600 |
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committer | Radhika Jagtap <radhika.jagtap@ARM.com> | 2015-12-07 16:42:15 -0600 |
commit | eb19fc29761a99ff7d5a5e4588866b487a2082ee (patch) | |
tree | 0d0caae1d24eb8e3bf7d7c34eadd7810e0106cae /src/cpu/o3/rename.hh | |
parent | bbcbe028fe904ec3f48b39e02c4a8fbc6f438699 (diff) | |
download | gem5-eb19fc29761a99ff7d5a5e4588866b487a2082ee.tar.xz |
probe: Add probe in Fetch, IEW, Rename and Commit
This patch adds probe points in Fetch, IEW, Rename and Commit stages as follows.
A probe point is added in the Fetch stage for probing when a fetch request is
sent. Notify is fired on the probe point when a request is sent succesfully in
the first attempt as well as on a retry attempt.
Probe points are added in the IEW stage when an instruction begins to execute
and when execution is complete. This points can be used for monitoring the
execution time of an instruction.
Probe points are added in the Rename stage to probe renaming of source and
destination registers and when there is squashing. These probe points can be
used to track register dependencies and remove when there is squashing.
A probe point for squashing is added in Commit to probe squashed instructions.
Diffstat (limited to 'src/cpu/o3/rename.hh')
-rw-r--r-- | src/cpu/o3/rename.hh | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh index a543cefb8..f8becc114 100644 --- a/src/cpu/o3/rename.hh +++ b/src/cpu/o3/rename.hh @@ -45,10 +45,12 @@ #define __CPU_O3_RENAME_HH__ #include <list> +#include <utility> #include "base/statistics.hh" #include "config/the_isa.hh" #include "cpu/timebuf.hh" +#include "sim/probe/probe.hh" struct DerivO3CPUParams; @@ -119,6 +121,16 @@ class DefaultRename /** Per-thread status. */ ThreadStatus renameStatus[Impl::MaxThreads]; + /** Probe points. */ + typedef typename std::pair<InstSeqNum, short int> SeqNumRegPair; + /** To probe when register renaming for an instruction is complete */ + ProbePointArg<DynInstPtr> *ppRename; + /** + * To probe when an instruction is squashed and the register mapping + * for it needs to be undone + */ + ProbePointArg<SeqNumRegPair> *ppSquashInRename; + public: /** DefaultRename constructor. */ DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params); @@ -129,6 +141,9 @@ class DefaultRename /** Registers statistics. */ void regStats(); + /** Registers probes. */ + void regProbePoints(); + /** Sets the main backwards communication time buffer pointer. */ void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); |