diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-01 17:12:43 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-01 17:12:43 -0700 |
| commit | abe18be544014bee31d586bf8b26ab5b622b70b7 (patch) | |
| tree | ad4059302f30b79257cb50cb8e51c5da38c6418c /src/cpu/o3/rename_impl.hh | |
| parent | edeb8f39a7c3cbcf428743aca3017fa42865b04a (diff) | |
| parent | d8501ec17c590a0c6f5be92e121381667ca726b6 (diff) | |
| download | gem5-abe18be544014bee31d586bf8b26ab5b622b70b7.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head
--HG--
extra : convert_revision : 8b0fbb6b1ea38d01d048381f18fd95ab63c4c0f1
Diffstat (limited to 'src/cpu/o3/rename_impl.hh')
| -rw-r--r-- | src/cpu/o3/rename_impl.hh | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 892eb12cf..782c0fe5f 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -355,9 +355,7 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is // a possible delay slot inst for different architectures // insts[tid].clear(); -#if THE_ISA == ALPHA_ISA - insts[tid].clear(); -#else +#if ISA_HAS_DELAY_SLOT DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until " "[sn:%i].\n",tid, squash_seq_num); ListIt ilist_it = insts[tid].begin(); @@ -369,14 +367,14 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) } ilist_it++; } +#else + insts[tid].clear(); #endif // Clear the skid buffer in case it has any data in it. // See comments above. // skidBuffer[tid].clear(); -#if THE_ISA == ALPHA_ISA - skidBuffer[tid].clear(); -#else +#if ISA_HAS_DELAY_SLOT DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions " "until [sn:%i].\n", tid, squash_seq_num); ListIt slist_it = skidBuffer[tid].begin(); @@ -388,6 +386,8 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) } slist_it++; } +#else + skidBuffer[tid].clear(); #endif doSquash(squash_seq_num, tid); } @@ -743,7 +743,7 @@ DefaultRename<Impl>::sortInsts() { int insts_from_decode = fromDecode->size; #ifdef DEBUG -#if THE_ISA == ALPHA_ISA +#if !ISA_HAS_DELAY_SLOT for (int i=0; i < numThreads; i++) assert(insts[i].empty()); #endif @@ -1182,10 +1182,10 @@ DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " "commit.\n", tid); -#if THE_ISA == ALPHA_ISA - InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; -#else +#if ISA_HAS_DELAY_SLOT InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum; +#else + InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; #endif squash(squashed_seq_num, tid); |