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| author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
|---|---|---|
| committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
| commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
| tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/o3/rename_impl.hh | |
| parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
| download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz | |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/o3/rename_impl.hh')
| -rw-r--r-- | src/cpu/o3/rename_impl.hh | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 6bfc7d952..38191ce36 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -65,7 +65,8 @@ DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) renameWidth(params->renameWidth), commitWidth(params->commitWidth), numThreads(params->numThreads), - maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) + maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs + + params->numPhysCCRegs) { // @todo: Make into a parameter. skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; @@ -974,6 +975,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) fpRenameLookups++; break; + case CCRegClass: + flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg); + renamed_reg = map->lookupCC(flat_rel_src_reg); + break; + case MiscRegClass: // misc regs don't get flattened flat_rel_src_reg = rel_src_reg; @@ -1034,6 +1040,12 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; break; + case CCRegClass: + flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg); + rename_result = map->renameCC(flat_rel_dest_reg); + flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base; + break; + case MiscRegClass: // misc regs don't get flattened flat_rel_dest_reg = rel_dest_reg; |