This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world

succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh!

Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS
ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... )

src/arch/alpha/isa/mem.isa:
    spacing
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
    Gabe really authored this
src/arch/mips/isa/decoder.isa:
    add StoreConditional Flag to instruction
src/arch/mips/isa/formats/basic.isa:
    Steven really did this file
src/arch/mips/isa/formats/branch.isa:
    fix bug for uncond/cond control
src/arch/mips/isa/formats/mem.isa:
    Adjust O3CPU memory access to use new memory model interface.
src/arch/mips/isa/formats/util.isa:
    update LoadStoreBase template
src/arch/mips/isa_traits.cc:
    update SERIALIZE partially
src/arch/mips/process.cc:
src/arch/mips/process.hh:
    no need for this for NOW. ASID/Virtual addressing handles it
src/arch/mips/regfile/misc_regfile.hh:
    add in clear() function and comments for future usage of special misc. regs
src/cpu/base_dyn_inst.hh:
    add in nextNPC variable and supporting functions.

    add isCondDelaySlot function

    Update predTaken and mispredicted functions
src/cpu/base_dyn_inst_impl.hh:
    init nextNPC
src/cpu/o3/SConscript:
    add MIPS files to compile
src/cpu/o3/alpha/thread_context.hh:
    no need for my name on this file
src/cpu/o3/bpred_unit_impl.hh:
    Update RAS appropriately for MIPS
src/cpu/o3/comm.hh:
    add some extra communication variables to aid in handling the
    delay slots
src/cpu/o3/commit.hh:
    minor name fix for nextNPC functions.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
    Fix necessary variables and functions for squashes with delay slots
src/cpu/o3/cpu.cc:
    Update function interface ...

    adjust removeInstsNotInROB function to recognize delay slots insts
src/cpu/o3/cpu.hh:
    update removeInstsNotInROB
src/cpu/o3/decode.hh:
    declare necessary variables for handling delay slot
src/cpu/o3/dyn_inst.hh:
    Add in MipsDynInst
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/rename.hh:
    declare necessary variables and adjust functions for handling delay slot
src/cpu/o3/inst_queue.hh:
src/cpu/simple/base.cc:
    no need for my name here
src/cpu/o3/isa_specific.hh:
    add in MIPS files
src/cpu/o3/scoreboard.hh:
    dont include alpha specific isa traits!
src/cpu/o3/thread_context.hh:
    no need for my name here, i just rearranged where the file goes
src/cpu/static_inst.hh:
    add isCondDelaySlot function
src/cpu/o3/mips/cpu.cc:
src/cpu/o3/mips/cpu.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/mips/dyn_inst.cc:
src/cpu/o3/mips/dyn_inst.hh:
src/cpu/o3/mips/dyn_inst_impl.hh:
src/cpu/o3/mips/impl.hh:
src/cpu/o3/mips/params.hh:
src/cpu/o3/mips/thread_context.cc:
src/cpu/o3/mips/thread_context.hh:
    MIPS file for O3CPU...mirrors ALPHA definition

--HG--
extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c

1 files changed, 55 insertions, 11 deletions

diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 805a72808..ee251de00 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Kevin Lim
+ *          Korey Sewell
  */
 
 #include <list>
@@ -318,7 +319,7 @@ DefaultRename<Impl>::takeOverFrom()
 
 template <class Impl>
 void
-DefaultRename<Impl>::squash(unsigned tid)
+DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
 {
     DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
 
@@ -341,19 +342,55 @@ DefaultRename<Impl>::squash(unsigned tid)
     unsigned squashCount = 0;
 
     for (int i=0; i<fromDecode->size; i++) {
-        if (fromDecode->insts[i]->threadNumber == tid) {
+        if (fromDecode->insts[i]->threadNumber == tid &&
+            fromDecode->insts[i]->seqNum > squash_seq_num) {
             fromDecode->insts[i]->setSquashed();
             wroteToTimeBuffer = true;
             squashCount++;
         }
+
     }
 
+    // Clear the instruction list and skid buffer in case they have any
+    // insts in them. Since we support multiple ISAs, we cant just:
+    // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
+    // a possible delay slot inst for different architectures
+    // insts[tid].clear();
+#if THE_ISA == ALPHA_ISA
     insts[tid].clear();
+#else
+    DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
+            "[sn:%i].\n",tid, squash_seq_num);
+    ListIt ilist_it = insts[tid].begin();
+    while (ilist_it != insts[tid].end()) {
+        if ((*ilist_it)->seqNum > squash_seq_num) {
+            (*ilist_it)->setSquashed();
+            DPRINTF(Rename, "Squashing incoming decode instruction, "
+                    "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
+        }
+        ilist_it++;
+    }
+#endif
 
     // Clear the skid buffer in case it has any data in it.
+    // See comments above.
+    //     skidBuffer[tid].clear();
+#if THE_ISA == ALPHA_ISA
     skidBuffer[tid].clear();
-
-    doSquash(tid);
+#else
+    DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
+            "until [sn:%i].\n", tid, squash_seq_num);
+    ListIt slist_it = skidBuffer[tid].begin();
+    while (slist_it != skidBuffer[tid].end()) {
+        if ((*slist_it)->seqNum > squash_seq_num) {
+            (*slist_it)->setSquashed();
+            DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
+                    "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
+        }
+        slist_it++;
+    }
+#endif
+    doSquash(squash_seq_num, tid);
 }
 
 template <class Impl>
@@ -572,7 +609,7 @@ DefaultRename<Impl>::renameInsts(unsigned tid)
         if (inst->isSquashed()) {
             DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
                     "squashed, skipping.\n",
-                    tid, inst->seqNum, inst->threadNumber,inst->readPC());
+                    tid, inst->seqNum, inst->readPC());
 
             ++renameSquashedInsts;
 
@@ -707,9 +744,11 @@ DefaultRename<Impl>::sortInsts()
 {
     int insts_from_decode = fromDecode->size;
 #ifdef DEBUG
+#if THE_ISA == ALPHA_ISA
     for (int i=0; i < numThreads; i++)
         assert(insts[i].empty());
 #endif
+#endif
     for (int i = 0; i < insts_from_decode; ++i) {
         DynInstPtr inst = fromDecode->insts[i];
         insts[inst->threadNumber].push_back(inst);
@@ -824,12 +863,10 @@ DefaultRename<Impl>::unblock(unsigned tid)
 
 template <class Impl>
 void
-DefaultRename<Impl>::doSquash(unsigned tid)
+DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
 {
     typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin();
 
-    InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
-
     // After a syscall squashes everything, the history buffer may be empty
     // but the ROB may still be squashing instructions.
     if (historyBuffer[tid].empty()) {
@@ -963,8 +1000,9 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
 
         historyBuffer[tid].push_front(hb_entry);
 
-        DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, "
-                "[sn:%lli].\n",tid,
+        DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
+                "(size=%i), [sn:%lli].\n",tid,
+                historyBuffer[tid].size(),
                 (*historyBuffer[tid].begin()).instSeqNum);
 
         // Tell the instruction to rename the appropriate destination
@@ -1143,7 +1181,13 @@ DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
         DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
                 "commit.\n", tid);
 
-        squash(tid);
+#if THE_ISA == ALPHA_ISA
+        InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
+#else
+        InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
+#endif
+
+        squash(squashed_seq_num, tid);
 
         return true;
     }