add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models

src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
    define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
    use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA

--HG--
extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a

1 files changed, 10 insertions, 10 deletions

diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 892eb12cf..782c0fe5f 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -355,9 +355,7 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
     // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
     // a possible delay slot inst for different architectures
     // insts[tid].clear();
-#if THE_ISA == ALPHA_ISA
-    insts[tid].clear();
-#else
+#if ISA_HAS_DELAY_SLOT
     DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
             "[sn:%i].\n",tid, squash_seq_num);
     ListIt ilist_it = insts[tid].begin();
@@ -369,14 +367,14 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
         }
         ilist_it++;
     }
+#else
+    insts[tid].clear();
 #endif
 
     // Clear the skid buffer in case it has any data in it.
     // See comments above.
     //     skidBuffer[tid].clear();
-#if THE_ISA == ALPHA_ISA
-    skidBuffer[tid].clear();
-#else
+#if ISA_HAS_DELAY_SLOT
     DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
             "until [sn:%i].\n", tid, squash_seq_num);
     ListIt slist_it = skidBuffer[tid].begin();
@@ -388,6 +386,8 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
         }
         slist_it++;
     }
+#else
+    skidBuffer[tid].clear();
 #endif
     doSquash(squash_seq_num, tid);
 }
@@ -743,7 +743,7 @@ DefaultRename<Impl>::sortInsts()
 {
     int insts_from_decode = fromDecode->size;
 #ifdef DEBUG
-#if THE_ISA == ALPHA_ISA
+#if !ISA_HAS_DELAY_SLOT
     for (int i=0; i < numThreads; i++)
         assert(insts[i].empty());
 #endif
@@ -1182,10 +1182,10 @@ DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
         DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
                 "commit.\n", tid);
 
-#if THE_ISA == ALPHA_ISA
-        InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
-#else
+#if ISA_HAS_DELAY_SLOT
         InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
+#else
+        InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
 #endif
 
         squash(squashed_seq_num, tid);