diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:43 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:43 -0400 |
| commit | 9bd017b8aee1432b78361da89ce4980dabb70084 (patch) | |
| tree | dd72d8882f825474a0a24297137e819212c8ec33 /src/cpu/o3/rename_impl.hh | |
| parent | c009d0eb2a02dddce6cca1033d73efde21445487 (diff) | |
| download | gem5-9bd017b8aee1432b78361da89ce4980dabb70084.tar.xz | |
cpu/o3: clean up scoreboard object
It had a bunch of fields (and associated constructor
parameters) thet it didn't really use, and the array
initialization was needlessly verbose.
Also just hardwired the getReg() method to aleays
return true for misc regs, rather than having an array
of bits that we always kept marked as ready.
Diffstat (limited to 'src/cpu/o3/rename_impl.hh')
| -rw-r--r-- | src/cpu/o3/rename_impl.hh | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 6e564abab..3ab0afe11 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -884,11 +884,6 @@ DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) // Put the renamed physical register back on the free list. freeList->addReg(hb_it->newPhysReg); - // Be sure to mark its register as ready if it's a misc register. - if (hb_it->newPhysReg >= maxPhysicalRegs) { - scoreboard->setReg(hb_it->newPhysReg); - } - historyBuffer[tid].erase(hb_it++); ++renameUndoneMaps; @@ -1050,8 +1045,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) rename_result = renameMap[tid]->rename(flat_dest_reg); //Mark Scoreboard entry as not ready - if (regIdxToClass(dest_reg) != MiscRegClass) - scoreboard->unsetReg(rename_result.first); + scoreboard->unsetReg(rename_result.first); DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " "reg %i.\n", tid, (int)flat_dest_reg, |