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authorNilay Vaish <nilay@cs.wisc.edu>2015-07-28 01:58:04 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-07-28 01:58:04 -0500
commitaafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch)
treed40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/cpu/o3/rename_impl.hh
parent608641e23c7f2288810c3f23a1a63790b664f2ab (diff)
downloadgem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz
revert 5af8f40d8f2c
Diffstat (limited to 'src/cpu/o3/rename_impl.hh')
-rw-r--r--src/cpu/o3/rename_impl.hh20
1 files changed, 4 insertions, 16 deletions
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 3da6fd4fa..43b7ba9aa 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -69,7 +69,7 @@ DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
commitWidth(params->commitWidth),
numThreads(params->numThreads),
maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs
- + params->numPhysCCRegs + params->numPhysVectorRegs)
+ + params->numPhysCCRegs)
{
if (renameWidth > Impl::MaxWidth)
fatal("renameWidth (%d) is larger than compiled limit (%d),\n"
@@ -635,8 +635,7 @@ DefaultRename<Impl>::renameInsts(ThreadID tid)
// to rename to. Otherwise block.
if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
inst->numFPDestRegs(),
- inst->numCCDestRegs(),
- inst->numVectorDestRegs())) {
+ inst->numCCDestRegs())) {
DPRINTF(Rename, "Blocking due to lack of free "
"physical registers to rename to.\n");
blockThisCycle = true;
@@ -1017,11 +1016,6 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
renamed_reg = map->lookupCC(flat_rel_src_reg);
break;
- case VectorRegClass:
- flat_rel_src_reg = tc->flattenVectorIndex(rel_src_reg);
- renamed_reg = map->lookupVector(flat_rel_src_reg);
- break;
-
case MiscRegClass:
// misc regs don't get flattened
flat_rel_src_reg = rel_src_reg;
@@ -1088,12 +1082,6 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base;
break;
- case VectorRegClass:
- flat_rel_dest_reg = tc->flattenVectorIndex(rel_dest_reg);
- rename_result = map->renameVector(flat_rel_dest_reg);
- flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Vector_Reg_Base;
- break;
-
case MiscRegClass:
// misc regs don't get flattened
flat_rel_dest_reg = rel_dest_reg;
@@ -1168,7 +1156,7 @@ inline int
DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid)
{
int num_free = freeEntries[tid].lqEntries -
- (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ);
+ (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ);
DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, "
"loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries,
loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ);
@@ -1180,7 +1168,7 @@ inline int
DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid)
{
int num_free = freeEntries[tid].sqEntries -
- (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ);
+ (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ);
DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, "
"stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries,
storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ);