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| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-20 17:32:12 +0800 |
| commit | 32986563546481d9ac17280cd0aadb39b87b9817 (patch) | |
| tree | a3acaa4ffdd3764d92dda1973e996ca9f6a09b76 /src/cpu/o3/rename_impl.hh | |
| parent | 0c50a0b4fe3956f9d2e08e75d47c9cbd79bf0268 (diff) | |
| download | gem5-32986563546481d9ac17280cd0aadb39b87b9817.tar.xz | |
invisispec-1.0 source
Diffstat (limited to 'src/cpu/o3/rename_impl.hh')
| -rw-r--r-- | src/cpu/o3/rename_impl.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index a295a8705..d4a6bb3b7 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -1368,7 +1368,8 @@ DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) // Mark a bit to say that I must serialize on the next instruction. serializeOnNextInst[tid] = true; return; - } + } + // Set the next instruction as serializing. inst_list.front()->setSerializeBefore(); |