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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:43 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:43 -0400 |
| commit | 219c423f1fb0f9a559bfa87f9812426d5e2c3e29 (patch) | |
| tree | 7980ae867c4642e710af7cd5d0ad7fe51c0b6687 /src/cpu/o3/rename_impl.hh | |
| parent | a830e63de71e5929b8ff8e334bc872faa9193a8b (diff) | |
| download | gem5-219c423f1fb0f9a559bfa87f9812426d5e2c3e29.tar.xz | |
cpu: rename *_DepTag constants to *_Reg_Base
Make these names more meaningful.
Specifically, made these substitutions:
s/FP_Base_DepTag/FP_Reg_Base/g;
s/Ctrl_Base_DepTag/Misc_Reg_Base/g;
s/Max_DepTag/Max_Reg_Index/g;
Diffstat (limited to 'src/cpu/o3/rename_impl.hh')
| -rw-r--r-- | src/cpu/o3/rename_impl.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 3ab0afe11..60a929551 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -953,7 +953,7 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) break; case FloatRegClass: - src_reg = src_reg - TheISA::FP_Base_DepTag; + src_reg = src_reg - TheISA::FP_Reg_Base; flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); @@ -961,7 +961,7 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) break; case MiscRegClass: - flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + + flat_src_reg = src_reg - TheISA::Misc_Reg_Base + TheISA::NumFloatRegs + TheISA::NumIntRegs; DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg); @@ -1018,7 +1018,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) break; case FloatRegClass: - dest_reg = dest_reg - TheISA::FP_Base_DepTag; + dest_reg = dest_reg - TheISA::FP_Reg_Base; flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); @@ -1028,7 +1028,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) case MiscRegClass: // Floating point and Miscellaneous registers need their indexes // adjusted to account for the expanded number of flattened int regs. - flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag + + flat_dest_reg = dest_reg - TheISA::Misc_Reg_Base + TheISA::NumIntRegs + TheISA::NumFloatRegs; DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg); |