cpu: Simplify the rename interface and use RegId

With the hierarchical RegId there are a lot of functions that are
redundant now.

The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.

Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702

1 files changed, 32 insertions, 70 deletions

diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index a92792639..9c9b030f5 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, 2014-2015 ARM Limited
+ * Copyright (c) 2010-2012, 2014-2016 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
@@ -985,8 +985,8 @@ DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
 
         DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), "
                 "[sn:%lli].\n",
-                tid, hb_it->prevPhysReg->regIdx,
-                RegClassStrings[hb_it->prevPhysReg->regClass],
+                tid, hb_it->prevPhysReg->index(),
+                hb_it->prevPhysReg->className(),
                 hb_it->instSeqNum);
 
         // Don't free special phys regs like misc and zero regs, which
@@ -1013,59 +1013,46 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
     // Get the architectual register numbers from the source and
     // operands, and redirect them to the right physical register.
     for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
-        RegId src_reg = inst->srcRegIdx(src_idx);
-        RegIndex flat_src_reg;
+        const RegId& src_reg = inst->srcRegIdx(src_idx);
         PhysRegIdPtr renamed_reg;
 
-        switch (src_reg.regClass) {
+        renamed_reg = map->lookup(tc->flattenRegId(src_reg));
+        switch (src_reg.classValue()) {
           case IntRegClass:
-            flat_src_reg = tc->flattenIntIndex(src_reg.regIdx);
-            renamed_reg = map->lookupInt(flat_src_reg);
             intRenameLookups++;
             break;
-
           case FloatRegClass:
-            flat_src_reg = tc->flattenFloatIndex(src_reg.regIdx);
-            renamed_reg = map->lookupFloat(flat_src_reg);
             fpRenameLookups++;
             break;
-
           case CCRegClass:
-            flat_src_reg = tc->flattenCCIndex(src_reg.regIdx);
-            renamed_reg = map->lookupCC(flat_src_reg);
-            break;
-
           case MiscRegClass:
-            // misc regs don't get flattened
-            flat_src_reg = src_reg.regIdx;
-            renamed_reg = map->lookupMisc(flat_src_reg);
             break;
 
           default:
-            panic("Invalid register class: %d.", src_reg.regClass);
+            panic("Invalid register class: %d.", src_reg.classValue());
         }
 
         DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i"
-                " (flattened %i), got phys reg %i (%s)\n", tid,
-                RegClassStrings[src_reg.regClass], src_reg.regIdx,
-                flat_src_reg, renamed_reg->regIdx,
-                RegClassStrings[renamed_reg->regClass]);
+                ", got phys reg %i (%s)\n", tid,
+                src_reg.className(), src_reg.index(),
+                renamed_reg->index(),
+                renamed_reg->className());
 
         inst->renameSrcReg(src_idx, renamed_reg);
 
         // See if the register is ready or not.
         if (scoreboard->getReg(renamed_reg)) {
             DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
-                    " is ready.\n", tid, renamed_reg->regIdx,
-                    renamed_reg->flatIdx,
-                    RegClassStrings[renamed_reg->regClass]);
+                    " is ready.\n", tid, renamed_reg->index(),
+                    renamed_reg->flatIndex(),
+                    renamed_reg->className());
 
             inst->markSrcRegReady(src_idx);
         } else {
             DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
-                    " is not ready.\n", tid, renamed_reg->regIdx,
-                    renamed_reg->flatIdx,
-                    RegClassStrings[renamed_reg->regClass]);
+                    " is not ready.\n", tid, renamed_reg->index(),
+                    renamed_reg->flatIndex(),
+                    renamed_reg->className());
         }
 
         ++renameRenameLookups;
@@ -1082,51 +1069,26 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
 
     // Rename the destination registers.
     for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
-        RegId dest_reg = inst->destRegIdx(dest_idx);
-        RegIndex flat_dest_reg;
+        const RegId& dest_reg = inst->destRegIdx(dest_idx);
         typename RenameMap::RenameInfo rename_result;
 
-        switch (dest_reg.regClass) {
-          case IntRegClass:
-            flat_dest_reg = tc->flattenIntIndex(dest_reg.regIdx);
-            rename_result = map->renameInt(flat_dest_reg);
-            break;
-
-          case FloatRegClass:
-            flat_dest_reg = tc->flattenFloatIndex(dest_reg.regIdx);
-            rename_result = map->renameFloat(flat_dest_reg);
-            break;
-
-          case CCRegClass:
-            flat_dest_reg = tc->flattenCCIndex(dest_reg.regIdx);
-            rename_result = map->renameCC(flat_dest_reg);
-            break;
-
-          case MiscRegClass:
-            // misc regs don't get flattened
-            flat_dest_reg = dest_reg.regIdx;
-            rename_result = map->renameMisc(dest_reg.regIdx);
-            break;
-
-          default:
-            panic("Invalid register class: %d.", dest_reg.regClass);
-        }
+        RegId flat_dest_regid = tc->flattenRegId(dest_reg);
 
-        RegId flat_uni_dest_reg(dest_reg.regClass, flat_dest_reg);
+        rename_result = map->rename(flat_dest_regid);
 
-        inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
+        inst->flattenDestReg(dest_idx, flat_dest_regid);
 
         // Mark Scoreboard entry as not ready
         scoreboard->unsetReg(rename_result.first);
 
         DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical "
-                "reg %i (%i).\n", tid, dest_reg.regIdx,
-                RegClassStrings[dest_reg.regClass],
-                rename_result.first->regIdx,
-                rename_result.first->flatIdx);
+                "reg %i (%i).\n", tid, dest_reg.index(),
+                dest_reg.className(),
+                rename_result.first->index(),
+                rename_result.first->flatIndex());
 
         // Record the rename information so that a history can be kept.
-        RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
+        RenameHistory hb_entry(inst->seqNum, flat_dest_regid,
                                rename_result.first,
                                rename_result.second);
 
@@ -1439,12 +1401,12 @@ DefaultRename<Impl>::dumpHistory()
             cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:"
                     " %i[%s] Old phys reg: %i[%s]\n",
                     (*buf_it).instSeqNum,
-                    RegClassStrings[(*buf_it).archReg.regClass],
-                    (*buf_it).archReg.regIdx,
-                    (*buf_it).newPhysReg->regIdx,
-                    RegClassStrings[(*buf_it).newPhysReg->regClass],
-                    (*buf_it).prevPhysReg->regIdx,
-                    RegClassStrings[(*buf_it).prevPhysReg->regClass]);
+                    (*buf_it).archReg.className(),
+                    (*buf_it).archReg.index(),
+                    (*buf_it).newPhysReg->index(),
+                    (*buf_it).newPhysReg->className(),
+                    (*buf_it).prevPhysReg->index(),
+                    (*buf_it).prevPhysReg->className());
 
             buf_it++;
         }