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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-19 18:26:42 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-19 18:26:42 -0700 |
| commit | f3f3747431e001dc6c80da5b6489516b610c22d6 (patch) | |
| tree | 24fcbc928df1619a82dbfd9ffa6d6f6809f509f6 /src/cpu/o3/rename_impl.hh | |
| parent | a54ae9f92b6000e8aaf5e056deaead8725c25a74 (diff) | |
| download | gem5-f3f3747431e001dc6c80da5b6489516b610c22d6.tar.xz | |
X86: Put in the foundation for x87 stack based fp registers.
--HG--
extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de
Diffstat (limited to 'src/cpu/o3/rename_impl.hh')
| -rw-r--r-- | src/cpu/o3/rename_impl.hh | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index d78de2c87..49c885753 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -959,9 +959,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) if (src_reg < TheISA::FP_Base_DepTag) { flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); + } else if (src_reg < TheISA::Ctrl_Base_DepTag) { + src_reg = src_reg - TheISA::FP_Base_DepTag; + flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg); + flat_src_reg += TheISA::NumIntRegs; } else { - // Floating point and Miscellaneous registers need their indexes - // adjusted to account for the expanded number of flattened int regs. flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg); } |