A couple of minor fixes.

1. Set CPU ID in all modes for the O3 CPU.
2. Use nextCycle() function to prevent phase drift in O3 CPU.
3. Remove assertion in rename map that is no longer true.

src/cpu/o3/alpha/cpu_builder.cc:
    Allow for CPU id in all modes, not just full system.  Also include a parameter that was left out by accident.
src/cpu/o3/alpha/cpu_impl.hh:
    Set the CPU ID properly.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces.
src/cpu/o3/rename_map.cc:
    Remove assertion that is no longer true.
tests/configs/o3-timing.py:
    Set CPU's id to 0.

--HG--
extra : convert_revision : 2b69c19adfce2adcc2d1939e89d702bd6674d5d5

1 files changed, 0 insertions, 2 deletions

diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index 620daf691..b436ec1c3 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -192,8 +192,6 @@ SimpleRenameMap::rename(RegIndex arch_reg)
         // known that the prev reg was outside the range of normal registers
         // so the free list can avoid adding it.
         prev_reg = renamed_reg;
-
-        assert(renamed_reg < numPhysicalRegs + numMiscRegs);
     }
 
     DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",