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authorGabe Black <gblack@eecs.umich.edu>2007-04-22 17:50:43 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-04-22 17:50:43 +0000
commitacc62514b1a4244182a7e5fad8ca03505389d94d (patch)
tree29e96f23f04f19c16a9fdf1f7ef5fa9d7f23b277 /src/cpu/o3/rename_map.cc
parentcea543576082ed860e8dae17519ace48e5b2c78a (diff)
downloadgem5-acc62514b1a4244182a7e5fad8ca03505389d94d.tar.xz
Make the floating point zero register special handling only apply for ALPHA.
--HG-- extra : convert_revision : 4f393a5471656b29cecbacfcb337992239775915
Diffstat (limited to 'src/cpu/o3/rename_map.cc')
-rw-r--r--src/cpu/o3/rename_map.cc4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index b436ec1c3..e6649ce3e 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -165,17 +165,21 @@ SimpleRenameMap::rename(RegIndex arch_reg)
// If it's not referencing the zero register, then rename the
// register.
+#if THE_ISA == ALPHA_ISA
if (arch_reg != floatZeroReg) {
+#endif
renamed_reg = freeList->getFloatReg();
floatRenameMap[arch_reg].physical_reg = renamed_reg;
assert(renamed_reg < numPhysicalRegs &&
renamed_reg >= numPhysicalIntRegs);
+#if THE_ISA == ALPHA_ISA
} else {
// Otherwise return the zero register so nothing bad happens.
renamed_reg = floatZeroReg;
}
+#endif
} else {
// Subtract off the base offset for miscellaneous registers.
arch_reg = arch_reg - numLogicalRegs;