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| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 43d833246fcfe092a0c08dde1fdf7e3d409d1af9 (patch) | |
| tree | 650b39da3cb6e6ee0b8692032f56cc4d975a548b /src/cpu/o3/rename_map.cc | |
| parent | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (diff) | |
| download | gem5-43d833246fcfe092a0c08dde1fdf7e3d409d1af9.tar.xz | |
cpu: Physical register structural + flat indexing
Mimic the changes done on the architectural register indexes on the
physical register indexes. This is specific to the O3 model. The
structure, called PhysRegId, contains a register class, a register
index and a flat register index. The flat register index is kept
because it is useful in some cases where the type of register is not
important (dependency graph and scoreboard for example). Instead
of directly using the structure, most of the code is working with
a const PhysRegId* (typedef to PhysRegIdPtr). The actual PhysRegId
objects are stored in the regFile.
Change-Id: Ic879a3cc608aa2f34e2168280faac1846de77667
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2701
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/o3/rename_map.cc')
| -rw-r--r-- | src/cpu/o3/rename_map.cc | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc index 6307b58de..4555946c2 100644 --- a/src/cpu/o3/rename_map.cc +++ b/src/cpu/o3/rename_map.cc @@ -60,11 +60,11 @@ SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, SimpleRenameMap::RenameInfo SimpleRenameMap::rename(RegIndex arch_reg) { - PhysRegIndex renamed_reg; + PhysRegIdPtr renamed_reg; // Record the current physical register that is renamed to the // requested architected register. - PhysRegIndex prev_reg = map[arch_reg]; + PhysRegIdPtr prev_reg = map[arch_reg]; // If it's not referencing the zero register, then rename the // register. @@ -74,12 +74,14 @@ SimpleRenameMap::rename(RegIndex arch_reg) map[arch_reg] = renamed_reg; } else { // Otherwise return the zero register so nothing bad happens. - assert(prev_reg == zeroReg); - renamed_reg = zeroReg; + assert(prev_reg->isZeroReg()); + renamed_reg = prev_reg; } - DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n", - arch_reg, renamed_reg, prev_reg); + DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was" + " %d (%d)\n", + arch_reg, renamed_reg->regIdx, renamed_reg->flatIdx, + prev_reg->regIdx, prev_reg->flatIdx); return RenameInfo(renamed_reg, prev_reg); } @@ -100,6 +102,7 @@ UnifiedRenameMap::init(PhysRegFile *_regFile, floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); + } @@ -126,7 +129,7 @@ UnifiedRenameMap::rename(RegId arch_reg) } -PhysRegIndex +PhysRegIdPtr UnifiedRenameMap::lookup(RegId arch_reg) const { switch (arch_reg.regClass) { @@ -149,7 +152,7 @@ UnifiedRenameMap::lookup(RegId arch_reg) const } void -UnifiedRenameMap::setEntry(RegId arch_reg, PhysRegIndex phys_reg) +UnifiedRenameMap::setEntry(RegId arch_reg, PhysRegIdPtr phys_reg) { switch (arch_reg.regClass) { case IntRegClass: |