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authorGabe Black <gblack@eecs.umich.edu>2007-01-03 00:52:30 -0500
committerGabe Black <gblack@eecs.umich.edu>2007-01-03 00:52:30 -0500
commit8840ebcb00f3988c781063e572b6df5742968f95 (patch)
treee9711f561dff45b31489a7fb539ed98660e26d0e /src/cpu/o3/rename_map.cc
parenta0e8aa6737f534a8e51d866728dd6dc59bef263d (diff)
parent7d7f3d0e99eca98a5659e73bce56d615f0ed4fc3 (diff)
downloadgem5-8840ebcb00f3988c781063e572b6df5742968f95.tar.xz
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : f4a05accb8fa24d425dd818b1b7f268378180e99
Diffstat (limited to 'src/cpu/o3/rename_map.cc')
-rw-r--r--src/cpu/o3/rename_map.cc5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index befbc3e8a..620daf691 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -180,6 +180,8 @@ SimpleRenameMap::rename(RegIndex arch_reg)
// Subtract off the base offset for miscellaneous registers.
arch_reg = arch_reg - numLogicalRegs;
+ DPRINTF(Rename, "Renamed misc reg %d\n", arch_reg);
+
// No renaming happens to the misc. registers. They are
// simply the registers that come after all the physical
// registers; thus take the base architected register and add
@@ -194,6 +196,9 @@ SimpleRenameMap::rename(RegIndex arch_reg)
assert(renamed_reg < numPhysicalRegs + numMiscRegs);
}
+ DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
+ arch_reg, renamed_reg, prev_reg);
+
return RenameInfo(renamed_reg, prev_reg);
}