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authorGabe Black <gblack@eecs.umich.edu>2007-05-09 20:50:46 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-05-09 20:50:46 -0700
commit4ad1b58fdd7cc9ba9704ae966a41c99fd0f1dbc9 (patch)
tree2c68db7cd94a457fff83fe8d4bd7c63a6de023c0 /src/cpu/o3/rename_map.cc
parent939cbd8201a4b0dfad6a56b5d9fb68cc2b23ae73 (diff)
parentc2ac0fd89b9928f653e1485b2432cd71b455d7c5 (diff)
downloadgem5-4ad1b58fdd7cc9ba9704ae966a41c99fd0f1dbc9.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into doughnut.mwconnections.com:/home/gblack/newmem-o3-micro --HG-- extra : convert_revision : 545b9e98eb1895f4b9e782224fb6615c71ed6323
Diffstat (limited to 'src/cpu/o3/rename_map.cc')
-rw-r--r--src/cpu/o3/rename_map.cc4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index b436ec1c3..e6649ce3e 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -165,17 +165,21 @@ SimpleRenameMap::rename(RegIndex arch_reg)
// If it's not referencing the zero register, then rename the
// register.
+#if THE_ISA == ALPHA_ISA
if (arch_reg != floatZeroReg) {
+#endif
renamed_reg = freeList->getFloatReg();
floatRenameMap[arch_reg].physical_reg = renamed_reg;
assert(renamed_reg < numPhysicalRegs &&
renamed_reg >= numPhysicalIntRegs);
+#if THE_ISA == ALPHA_ISA
} else {
// Otherwise return the zero register so nothing bad happens.
renamed_reg = floatZeroReg;
}
+#endif
} else {
// Subtract off the base offset for miscellaneous registers.
arch_reg = arch_reg - numLogicalRegs;