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author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
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committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/o3/rename_map.cc | |
parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/o3/rename_map.cc')
-rw-r--r-- | src/cpu/o3/rename_map.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc index ecee4c721..d816bf1fd 100644 --- a/src/cpu/o3/rename_map.cc +++ b/src/cpu/o3/rename_map.cc @@ -97,6 +97,8 @@ UnifiedRenameMap::init(PhysRegFile *_regFile, intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); + + ccMap.init(TheISA::NumFloatRegs, &(freeList->ccList), (RegIndex)-1); } @@ -112,6 +114,9 @@ UnifiedRenameMap::rename(RegIndex arch_reg) case FloatRegClass: return renameFloat(rel_arch_reg); + case CCRegClass: + return renameCC(rel_arch_reg); + case MiscRegClass: return renameMisc(rel_arch_reg); @@ -134,6 +139,9 @@ UnifiedRenameMap::lookup(RegIndex arch_reg) const case FloatRegClass: return lookupFloat(rel_arch_reg); + case CCRegClass: + return lookupCC(rel_arch_reg); + case MiscRegClass: return lookupMisc(rel_arch_reg); @@ -155,6 +163,9 @@ UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg) case FloatRegClass: return setFloatEntry(rel_arch_reg, phys_reg); + case CCRegClass: + return setCCEntry(rel_arch_reg, phys_reg); + case MiscRegClass: // Misc registers do not actually rename, so don't change // their mappings. We end up here when a commit or squash |