cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.

1 files changed, 12 insertions, 0 deletions

diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index b0232df20..27ddd8c63 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -99,6 +99,9 @@ UnifiedRenameMap::init(PhysRegFile *_regFile,
     floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
 
     ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
+
+    vectorMap.init(TheISA::NumVectorRegs, &(freeList->vectorList),
+                   (RegIndex)-1);
 }
 
 
@@ -117,6 +120,9 @@ UnifiedRenameMap::rename(RegIndex arch_reg)
       case CCRegClass:
         return renameCC(rel_arch_reg);
 
+      case VectorRegClass:
+        return renameVector(rel_arch_reg);
+
       case MiscRegClass:
         return renameMisc(rel_arch_reg);
 
@@ -142,6 +148,9 @@ UnifiedRenameMap::lookup(RegIndex arch_reg) const
       case CCRegClass:
         return lookupCC(rel_arch_reg);
 
+      case VectorRegClass:
+        return lookupVector(rel_arch_reg);
+
       case MiscRegClass:
         return lookupMisc(rel_arch_reg);
 
@@ -166,6 +175,9 @@ UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
       case CCRegClass:
         return setCCEntry(rel_arch_reg, phys_reg);
 
+      case VectorRegClass:
+        return setVectorEntry(rel_arch_reg, phys_reg);
+
       case MiscRegClass:
         // Misc registers do not actually rename, so don't change
         // their mappings.  We end up here when a commit or squash