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author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
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committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/o3/rename_map.hh | |
parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/o3/rename_map.hh')
-rw-r--r-- | src/cpu/o3/rename_map.hh | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh index c989fb88f..751c39f52 100644 --- a/src/cpu/o3/rename_map.hh +++ b/src/cpu/o3/rename_map.hh @@ -163,6 +163,9 @@ class UnifiedRenameMap */ PhysRegFile *regFile; + /** The condition-code register rename map */ + SimpleRenameMap ccMap; + public: typedef TheISA::RegIndex RegIndex; @@ -214,6 +217,17 @@ class UnifiedRenameMap } /** + * Perform rename() on a condition-code register, given a relative + * condition-code register index. + */ + RenameInfo renameCC(RegIndex rel_arch_reg) + { + RenameInfo info = ccMap.rename(rel_arch_reg); + assert(regFile->isCCPhysReg(info.first)); + return info; + } + + /** * Perform rename() on a misc register, given a relative * misc register index. */ @@ -260,6 +274,17 @@ class UnifiedRenameMap } /** + * Perform lookup() on a condition-code register, given a relative + * condition-code register index. + */ + PhysRegIndex lookupCC(RegIndex rel_arch_reg) const + { + PhysRegIndex phys_reg = ccMap.lookup(rel_arch_reg); + assert(regFile->isCCPhysReg(phys_reg)); + return phys_reg; + } + + /** * Perform lookup() on a misc register, given a relative * misc register index. */ @@ -302,6 +327,16 @@ class UnifiedRenameMap } /** + * Perform setEntry() on a condition-code register, given a relative + * condition-code register index. + */ + void setCCEntry(RegIndex arch_reg, PhysRegIndex phys_reg) + { + assert(regFile->isCCPhysReg(phys_reg)); + ccMap.setEntry(arch_reg, phys_reg); + } + + /** * Return the minimum number of free entries across all of the * register classes. The minimum is used so we guarantee that * this number of entries is available regardless of which class |