diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/cpu/o3/rename_map.hh | |
parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz |
revert 5af8f40d8f2c
Diffstat (limited to 'src/cpu/o3/rename_map.hh')
-rw-r--r-- | src/cpu/o3/rename_map.hh | 41 |
1 files changed, 2 insertions, 39 deletions
diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh index 37487c3d3..9d91f232e 100644 --- a/src/cpu/o3/rename_map.hh +++ b/src/cpu/o3/rename_map.hh @@ -178,9 +178,6 @@ class UnifiedRenameMap /** The condition-code register rename map */ SimpleRenameMap ccMap; - /** The vector register rename map */ - SimpleRenameMap vectorMap; - public: typedef TheISA::RegIndex RegIndex; @@ -243,17 +240,6 @@ class UnifiedRenameMap } /** - * Perform rename() on a vector register, given a relative vector register - * index. - */ - RenameInfo renameVector(RegIndex rel_arch_reg) - { - RenameInfo info = vectorMap.rename(rel_arch_reg); - assert(regFile->isVectorPhysReg(info.first)); - return info; - } - - /** * Perform rename() on a misc register, given a relative * misc register index. */ @@ -311,17 +297,6 @@ class UnifiedRenameMap } /** - * Perform lookup() on a vector register, given a relative - * vector register index. - */ - PhysRegIndex lookupVector(RegIndex rel_arch_reg) const - { - PhysRegIndex phys_reg = vectorMap.lookup(rel_arch_reg); - assert(regFile->isVectorPhysReg(phys_reg)); - return phys_reg; - } - - /** * Perform lookup() on a misc register, given a relative * misc register index. */ @@ -374,16 +349,6 @@ class UnifiedRenameMap } /** - * Perform setEntry() on a vector register, given a relative vector - * register index. - */ - void setVectorEntry(RegIndex arch_reg, PhysRegIndex phys_reg) - { - assert(regFile->isVectorPhysReg(phys_reg)); - vectorMap.setEntry(arch_reg, phys_reg); - } - - /** * Return the minimum number of free entries across all of the * register classes. The minimum is used so we guarantee that * this number of entries is available regardless of which class @@ -397,13 +362,11 @@ class UnifiedRenameMap /** * Return whether there are enough registers to serve the request. */ - bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t ccRegs, - uint32_t vectorRegs) const + bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t ccRegs) const { return intRegs <= intMap.numFreeEntries() && floatRegs <= floatMap.numFreeEntries() && - ccRegs <= ccMap.numFreeEntries() && - vectorRegs <= vectorMap.numFreeEntries(); + ccRegs <= ccMap.numFreeEntries(); } }; |