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| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-20 22:07:22 +0800 |
| commit | 07efd7c18c427304bc42c9b03ac60adf9967a985 (patch) | |
| tree | 1e49a43315c850dd18d035f6c84034030090a0d2 /src/cpu/o3/rob.hh | |
| parent | 6379bebd41899ca74ac146e8073aee0bd1781b3f (diff) | |
| download | gem5-07efd7c18c427304bc42c9b03ac60adf9967a985.tar.xz | |
invisispec-1.0 source
Diffstat (limited to 'src/cpu/o3/rob.hh')
| -rw-r--r-- | src/cpu/o3/rob.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh index ad7a6d6e7..37de88a67 100644 --- a/src/cpu/o3/rob.hh +++ b/src/cpu/o3/rob.hh @@ -206,6 +206,10 @@ class ROB /** Updates the tail instruction with the new youngest instruction. */ void updateTail(); + /** [SafeSpce] Updates load instructions visible condition + * set isPrevInstsCompleted and isPrevBrsResolved. */ + void updateVisibleState(); + /** Reads the PC of the oldest head instruction. */ // uint64_t readHeadPC(); |