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author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-18 15:46:57 +0800 |
commit | 970e6b3f8313c5ffc10b5cd84d2d471746b15999 (patch) | |
tree | aa3b4a369675d9c4fb019db3a0882652204cf63b /src/cpu/o3/rob.hh | |
parent | 497ebfe98578b71d22f979b848c4b873f05ec6ee (diff) | |
download | gem5-970e6b3f8313c5ffc10b5cd84d2d471746b15999.tar.xz |
invisispec-1.0 source
Diffstat (limited to 'src/cpu/o3/rob.hh')
-rw-r--r-- | src/cpu/o3/rob.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh index 1c3cc2815..7024d9920 100644 --- a/src/cpu/o3/rob.hh +++ b/src/cpu/o3/rob.hh @@ -212,6 +212,10 @@ class ROB /** Updates the tail instruction with the new youngest instruction. */ void updateTail(); + /** [SafeSpce] Updates load instructions visible condition + * set isPrevInstsCompleted and isPrevBrsResolved. */ + void updateVisibleState(); + /** Reads the PC of the oldest head instruction. */ // uint64_t readHeadPC(); |