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| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-20 17:32:12 +0800 |
| commit | 32986563546481d9ac17280cd0aadb39b87b9817 (patch) | |
| tree | a3acaa4ffdd3764d92dda1973e996ca9f6a09b76 /src/cpu/o3/rob.hh | |
| parent | 0c50a0b4fe3956f9d2e08e75d47c9cbd79bf0268 (diff) | |
| download | gem5-32986563546481d9ac17280cd0aadb39b87b9817.tar.xz | |
invisispec-1.0 source
Diffstat (limited to 'src/cpu/o3/rob.hh')
| -rw-r--r-- | src/cpu/o3/rob.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh index 1896e62a4..b5fc5c0fb 100644 --- a/src/cpu/o3/rob.hh +++ b/src/cpu/o3/rob.hh @@ -212,6 +212,10 @@ class ROB /** Updates the tail instruction with the new youngest instruction. */ void updateTail(); + /** [SafeSpce] Updates load instructions visible condition + * set isPrevInstsCompleted and isPrevBrsResolved. */ + void updateVisibleState(); + /** Reads the PC of the oldest head instruction. */ // uint64_t readHeadPC(); |