summaryrefslogtreecommitdiff
path: root/src/cpu/o3/rob_impl.hh
diff options
context:
space:
mode:
authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-01-07 13:05:46 -0500
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-01-07 13:05:46 -0500
commit1814a85a055732baf98fd030441bb4c5c5db9bdc (patch)
tree33dd6adc62342a55ac3b0f4dbe9fdb9d82faa323 /src/cpu/o3/rob_impl.hh
parent9e8003148f78811e600e51a900f96b71cb525b60 (diff)
downloadgem5-1814a85a055732baf98fd030441bb4c5c5db9bdc.tar.xz
cpu: Rewrite O3 draining to avoid stopping in microcode
Previously, the O3 CPU could stop in the middle of a microcode sequence. This patch makes sure that the pipeline stops when it has committed a normal instruction or exited from a microcode sequence. Additionally, it makes sure that the pipeline has no instructions in flight when it is drained, which should make draining more robust. Draining is controlled in the commit stage, which checks if the next PC after a committed instruction is in microcode. If this isn't the case, it requests a squash of all instructions after that the instruction that just committed and immediately signals a drain stall to the fetch stage. The CPU then continues to execute until the pipeline and all associated buffers are empty.
Diffstat (limited to 'src/cpu/o3/rob_impl.hh')
-rw-r--r--src/cpu/o3/rob_impl.hh52
1 files changed, 29 insertions, 23 deletions
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index ee4a9e576..5f62ce539 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -47,12 +59,6 @@ ROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
numInstsInROB(0),
numThreads(_numThreads)
{
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- squashedSeqNum[tid] = 0;
- doneSquashing[tid] = true;
- threadEntries[tid] = 0;
- }
-
std::string policy = _smtROBPolicy;
//Convert string to lowercase
@@ -95,10 +101,20 @@ ROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
"Partitioned, Threshold}");
}
- // Set the per-thread iterators to the end of the instruction list.
- for (ThreadID tid = 0; tid < numThreads; tid++) {
+ resetState();
+}
+
+template <class Impl>
+void
+ROB<Impl>::resetState()
+{
+ for (ThreadID tid = 0; tid < numThreads; tid++) {
+ doneSquashing[tid] = true;
+ threadEntries[tid] = 0;
squashIt[tid] = instList[tid].end();
+ squashedSeqNum[tid] = 0;
}
+ numInstsInROB = 0;
// Initialize the "universal" ROB head & tail point to invalid
// pointers
@@ -123,28 +139,18 @@ ROB<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
template <class Impl>
void
-ROB<Impl>::switchOut()
+ROB<Impl>::drainSanityCheck() const
{
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- instList[tid].clear();
- }
+ for (ThreadID tid = 0; tid < numThreads; tid++)
+ assert(instList[tid].empty());
+ assert(isEmpty());
}
template <class Impl>
void
ROB<Impl>::takeOverFrom()
{
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- doneSquashing[tid] = true;
- threadEntries[tid] = 0;
- squashIt[tid] = instList[tid].end();
- }
- numInstsInROB = 0;
-
- // Initialize the "universal" ROB head & tail point to invalid
- // pointers
- head = instList[0].end();
- tail = instList[0].end();
+ resetState();
}
template <class Impl>