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authorGabe Black <gblack@eecs.umich.edu>2006-12-07 18:49:10 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-12-07 18:49:10 -0500
commit97cdd5198b9c1a5b881833a71f24a22430a2b07b (patch)
treef9c62ffa317cdbf683f00d265a4762270813bd85 /src/cpu/o3/sparc/cpu.hh
parent0f8fd5fd689a3631a5896a1c098e6e561aa6a80e (diff)
downloadgem5-97cdd5198b9c1a5b881833a71f24a22430a2b07b.tar.xz
Compilation fixes
--HG-- extra : convert_revision : 974e91a960251a35d5ebb76c7e6c7ac330339896
Diffstat (limited to 'src/cpu/o3/sparc/cpu.hh')
-rw-r--r--src/cpu/o3/sparc/cpu.hh18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/cpu/o3/sparc/cpu.hh b/src/cpu/o3/sparc/cpu.hh
index 73c859367..08ebd2710 100644
--- a/src/cpu/o3/sparc/cpu.hh
+++ b/src/cpu/o3/sparc/cpu.hh
@@ -128,6 +128,24 @@ class SparcO3CPU : public FullO3CPU<Impl>
*/
void squashFromTC(unsigned tid);
+#if FULL_SYSTEM
+ /** Posts an interrupt. */
+ void post_interrupt(int int_num, int index);
+ /** HW return from error interrupt. */
+ Fault hwrei(unsigned tid);
+
+ bool simPalCheck(int palFunc, unsigned tid);
+
+ /** Returns the Fault for any valid interrupt. */
+ Fault getInterrupts();
+
+ /** Processes any an interrupt fault. */
+ void processInterrupts(Fault interrupt);
+
+ /** Halts the CPU. */
+ void halt() { panic("Halt not implemented!\n"); }
+#endif
+
/** Traps to handle given fault. */
void trap(Fault fault, unsigned tid);