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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-22 16:13:53 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-22 16:13:53 -0700 |
| commit | ed1db23b414a372a012d406d5a684775f00baa11 (patch) | |
| tree | 1c706f022e2b84be0a01e5bc577075ba30276011 /src/cpu/o3/sparc/cpu_impl.hh | |
| parent | 4d1bcbcd36e5735e76b38abb151de716c31a2272 (diff) | |
| parent | 16c1b5484f576b6aebea9ab5ffab4ea64f080de0 (diff) | |
| download | gem5-ed1db23b414a372a012d406d5a684775f00baa11.tar.xz | |
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision : aa50af3094f5d459f75b514179b6e3ec5e0bf1df
Diffstat (limited to 'src/cpu/o3/sparc/cpu_impl.hh')
| -rw-r--r-- | src/cpu/o3/sparc/cpu_impl.hh | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 50d980f55..2e398577e 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -272,7 +272,10 @@ SparcO3CPU<Impl>::getSyscallArg(int i, int tid) { TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), SparcISA::ArgumentReg0 + i); - return this->readArchIntReg(idx, tid); + TheISA::IntReg val = this->readArchIntReg(idx, tid); + if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) + val = bits(val, 31, 0); + return val; } template <class Impl> |