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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-06 11:39:49 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-06 11:39:49 -0500 |
| commit | f04fcf58f1dc7adcf67e19ca00ff741775982dfa (patch) | |
| tree | cd4ee635a2df77f71812475371a3006e7e8c8436 /src/cpu/o3/sparc/cpu_impl.hh | |
| parent | 07a4e2cd36c35ab7b6be356d9bcf3b58b5ef6794 (diff) | |
| download | gem5-f04fcf58f1dc7adcf67e19ca00ff741775982dfa.tar.xz | |
Got rid of some typedefs and moved the tlbs into the base o3 cpu.
--HG--
extra : convert_revision : dcd1d2a64fd91aded15c8c763a78b4eebf421870
Diffstat (limited to 'src/cpu/o3/sparc/cpu_impl.hh')
| -rw-r--r-- | src/cpu/o3/sparc/cpu_impl.hh | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index f92d863cc..4a194cbda 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -55,12 +55,7 @@ #endif template <class Impl> -SparcO3CPU<Impl>::SparcO3CPU(Params *params) -#if FULL_SYSTEM - : FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb) -#else - : FullO3CPU<Impl>(params) -#endif +SparcO3CPU<Impl>::SparcO3CPU(Params *params) : FullO3CPU<Impl>(params) { DPRINTF(O3CPU, "Creating SparcO3CPU object.\n"); @@ -172,15 +167,16 @@ SparcO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid) template <class Impl> void -SparcO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) +SparcO3CPU<Impl>::setMiscReg(int misc_reg, + const SparcISA::MiscReg &val, unsigned tid) { this->regFile.setMiscReg(misc_reg, val, tid); } template <class Impl> void -SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val, - unsigned tid) +SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, + const SparcISA::MiscReg &val, unsigned tid) { this->regFile.setMiscRegWithEffect(misc_reg, val, tid); } @@ -285,16 +281,16 @@ template <class Impl> TheISA::IntReg SparcO3CPU<Impl>::getSyscallArg(int i, int tid) { - IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), + TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), SparcISA::ArgumentReg0 + i); return this->readArchIntReg(idx, tid); } template <class Impl> void -SparcO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid) +SparcO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) { - IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), + TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), SparcISA::ArgumentReg0 + i); this->setArchIntReg(idx, val, tid); } |