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author | Nathan Binkert <nate@binkert.org> | 2007-07-26 23:15:49 -0700 |
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committer | Nathan Binkert <nate@binkert.org> | 2007-07-26 23:15:49 -0700 |
commit | f0fef8f850b0c5aa73337ca11b26169163b2b2e1 (patch) | |
tree | d49d3492618ee85717554cddbe62cba1b5e7fb9c /src/cpu/o3/sparc/cpu_impl.hh | |
parent | 6b73ff43ff58502c80050c7aeff5a08a4ce61f87 (diff) | |
parent | cda354b07035f73a3b220f89014721300d36a815 (diff) | |
download | gem5-f0fef8f850b0c5aa73337ca11b26169163b2b2e1.tar.xz |
Merge python and x86 changes with cache branch
--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233
Diffstat (limited to 'src/cpu/o3/sparc/cpu_impl.hh')
-rw-r--r-- | src/cpu/o3/sparc/cpu_impl.hh | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 2e398577e..068057fc0 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -270,8 +270,9 @@ template <class Impl> TheISA::IntReg SparcO3CPU<Impl>::getSyscallArg(int i, int tid) { + assert(i < TheISA::NumArgumentRegs); TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg0 + i); + SparcISA::ArgumentReg[i]); TheISA::IntReg val = this->readArchIntReg(idx, tid); if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) val = bits(val, 31, 0); @@ -282,8 +283,9 @@ template <class Impl> void SparcO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) { + assert(i < TheISA::NumArgumentRegs); TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg0 + i); + SparcISA::ArgumentReg[i]); this->setArchIntReg(idx, val, tid); } |