Initial changes to get O3 working with SPARC

src/arch/sparc/process.cc:
    MachineBytes doesn't exist any more.
src/arch/sparc/regfile.cc:
    Add in the miscRegFile for good measure.
src/cpu/o3/isa_specific.hh:
    Add in a section for SPARC
src/cpu/o3/sparc/cpu.cc:
src/cpu/o3/sparc/cpu.hh:
src/cpu/o3/sparc/cpu_builder.cc:
src/cpu/o3/sparc/cpu_impl.hh:
src/cpu/o3/sparc/dyn_inst.cc:
src/cpu/o3/sparc/dyn_inst.hh:
src/cpu/o3/sparc/dyn_inst_impl.hh:
src/cpu/o3/sparc/impl.hh:
src/cpu/o3/sparc/params.hh:
src/cpu/o3/sparc/thread_context.cc:
src/cpu/o3/sparc/thread_context.hh:
    Sparc version of this file.

--HG--
extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4

1 files changed, 92 insertions, 0 deletions

diff --git a/src/cpu/o3/sparc/impl.hh b/src/cpu/o3/sparc/impl.hh
new file mode 100644
index 000000000..0a970c2f0
--- /dev/null
+++ b/src/cpu/o3/sparc/impl.hh
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __CPU_O3_SPARC_IMPL_HH__
+#define __CPU_O3_SPARC_IMPL_HH__
+
+#include "arch/sparc/isa_traits.hh"
+
+#include "cpu/o3/sparc/params.hh"
+#include "cpu/o3/cpu_policy.hh"
+
+
+// Forward declarations.
+template <class Impl>
+class SparcDynInst;
+
+template <class Impl>
+class SparcO3CPU;
+
+/** Implementation specific struct that defines several key types to the
+ *  CPU, the stages within the CPU, the time buffers, and the DynInst.
+ *  The struct defines the ISA, the CPU policy, the specific DynInst, the
+ *  specific O3CPU, and all of the structs from the time buffers to do
+ *  communication.
+ *  This is one of the key things that must be defined for each hardware
+ *  specific CPU implementation.
+ */
+struct SparcSimpleImpl
+{
+    /** The type of MachInst. */
+    typedef TheISA::MachInst MachInst;
+
+    /** The CPU policy to be used, which defines all of the CPU stages. */
+    typedef SimpleCPUPolicy<SparcSimpleImpl> CPUPol;
+
+    /** The DynInst type to be used. */
+    typedef SparcDynInst<SparcSimpleImpl> DynInst;
+
+    /** The refcounted DynInst pointer to be used.  In most cases this is
+     *  what should be used, and not DynInst *.
+     */
+    typedef RefCountingPtr<DynInst> DynInstPtr;
+
+    /** The O3CPU type to be used. */
+    typedef SparcO3CPU<SparcSimpleImpl> O3CPU;
+
+    /** Same typedef, but for CPUType.  BaseDynInst may not always use
+     * an O3 CPU, so it's clearer to call it CPUType instead in that
+     * case.
+     */
+    typedef O3CPU CPUType;
+
+    /** The Params to be passed to each stage. */
+    typedef SparcSimpleParams Params;
+
+    enum {
+      MaxWidth = 8,
+      MaxThreads = 4
+    };
+};
+
+/** The O3Impl to be used. */
+typedef SparcSimpleImpl O3CPUImpl;
+
+#endif // __CPU_O3_SPARC_IMPL_HH__