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author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-06 05:56:34 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-06 05:56:34 -0500 |
commit | 1d7d7df315e3bd9ddb3eedfed7f612e83778c252 (patch) | |
tree | c4b06b2e7a4cf3267929c81c73dc23595513e6a7 /src/cpu/o3/sparc | |
parent | 156cf0db51e48acf12d1d3ca36c9827fea0e6b7d (diff) | |
download | gem5-1d7d7df315e3bd9ddb3eedfed7f612e83778c252.tar.xz |
Make syscalls flatten their register indices, and also call into the ISA's setSyscallReturn function rather than having a duplicated one.
--HG--
extra : convert_revision : 1e83ef629a7fd143f2e35e68abaa56f81d6b9d9e
Diffstat (limited to 'src/cpu/o3/sparc')
-rw-r--r-- | src/cpu/o3/sparc/cpu_impl.hh | 25 |
1 files changed, 7 insertions, 18 deletions
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 536a620bf..f92d863cc 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -285,35 +285,24 @@ template <class Impl> TheISA::IntReg SparcO3CPU<Impl>::getSyscallArg(int i, int tid) { - return this->readArchIntReg(SparcISA::ArgumentReg0 + i, tid); + IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), + SparcISA::ArgumentReg0 + i); + return this->readArchIntReg(idx, tid); } template <class Impl> void SparcO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid) { - this->setArchIntReg(SparcISA::ArgumentReg0 + i, val, tid); + IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), + SparcISA::ArgumentReg0 + i); + this->setArchIntReg(idx, val, tid); } template <class Impl> void SparcO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) { - // check for error condition. SPARC syscall convention is to - // indicate success/failure in reg the carry bit of the ccr - // and put the return value itself in the standard return value reg (). - if (return_value.successful()) { - // no error, clear XCC.C - this->setMiscReg(SparcISA::MISCREG_CCR, - this->readMiscReg(SparcISA::MISCREG_CCR, tid) & 0xEE, tid); - this->setArchIntReg(SparcISA::ReturnValueReg, - return_value.value(), tid); - } else { - // got an error, set XCC.C - this->setMiscReg(SparcISA::MISCREG_CCR, - this->readMiscReg(SparcISA::MISCREG_CCR, tid) | 0x11, tid); - this->setArchIntReg(SparcISA::ReturnValueReg, - return_value.value(), tid); - } + TheISA::setSyscallReturn(return_value, this->tcBase(tid)); } #endif |