*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b

3 files changed, 24 insertions, 24 deletions

diff --git a/src/cpu/o3/sparc/cpu.hh b/src/cpu/o3/sparc/cpu.hh
index 08ebd2710..7b932e429 100644
--- a/src/cpu/o3/sparc/cpu.hh
+++ b/src/cpu/o3/sparc/cpu.hh
@@ -106,20 +106,20 @@ class SparcO3CPU : public FullO3CPU<Impl>
 
 #endif
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
+    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val,
+    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
             unsigned tid);
 
     /** Initiates a squash of all in-flight instructions for a given
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh
index c039a8fec..a425a8a56 100644
--- a/src/cpu/o3/sparc/cpu_impl.hh
+++ b/src/cpu/o3/sparc/cpu_impl.hh
@@ -153,32 +153,32 @@ SparcO3CPU<Impl>::regStats()
 
 template <class Impl>
 TheISA::MiscReg
-SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
+SparcO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscReg(misc_reg, tid);
+    return this->regFile.readMiscRegNoEffect(misc_reg, tid);
 }
 
 template <class Impl>
 TheISA::MiscReg
-SparcO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
+SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscRegWithEffect(misc_reg, tid);
+    return this->regFile.readMiscReg(misc_reg, tid);
 }
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setMiscReg(int misc_reg,
+SparcO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
         const SparcISA::MiscReg &val, unsigned tid)
 {
-    this->regFile.setMiscReg(misc_reg, val, tid);
+    this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
 }
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg,
+SparcO3CPU<Impl>::setMiscReg(int misc_reg,
         const SparcISA::MiscReg &val, unsigned tid)
 {
-    this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+    this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/sparc/dyn_inst.hh b/src/cpu/o3/sparc/dyn_inst.hh
index 4314488b5..bd61b0384 100644
--- a/src/cpu/o3/sparc/dyn_inst.hh
+++ b/src/cpu/o3/sparc/dyn_inst.hh
@@ -77,39 +77,39 @@ class SparcDynInst : public BaseDynInst<Impl>
 
   public:
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscReg(int misc_reg)
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg)
     {
-        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
+        return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
     }
 
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegWithEffect(int misc_reg)
+    TheISA::MiscReg readMiscReg(int misc_reg)
     {
-        return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
+        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
     }
 
     /** Sets a misc. register. */
-    void setMiscReg(int misc_reg, const TheISA::MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val)
     {
         this->instResult.integer = val;
-        return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
+        return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
     }
 
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val)
+    void setMiscReg(int misc_reg, const TheISA::MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(misc_reg, val,
+        return this->cpu->setMiscReg(misc_reg, val,
                                                this->threadNumber);
     }
 
     /** Reads a miscellaneous register. */
     TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
-        return this->cpu->readMiscReg(
+        return this->cpu->readMiscRegNoEffect(
                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 this->threadNumber);
     }
@@ -119,7 +119,7 @@ class SparcDynInst : public BaseDynInst<Impl>
      */
     TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
     {
-        return this->cpu->readMiscRegWithEffect(
+        return this->cpu->readMiscReg(
                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 this->threadNumber);
     }
@@ -129,7 +129,7 @@ class SparcDynInst : public BaseDynInst<Impl>
             int idx, const TheISA::MiscReg &val)
     {
         this->instResult.integer = val;
-        return this->cpu->setMiscReg(
+        return this->cpu->setMiscRegNoEffect(
                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 val, this->threadNumber);
     }
@@ -140,7 +140,7 @@ class SparcDynInst : public BaseDynInst<Impl>
     void setMiscRegOperandWithEffect(
             const StaticInst *si, int idx, const TheISA::MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(
+        return this->cpu->setMiscReg(
                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 val, this->threadNumber);
     }